Lines Matching refs:tn
449 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
456 layout = devm_kzalloc(tn->dev, sizeof(*layout), GFP_KERNEL);
490 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
492 if (tn->use_status) {
493 tn->use_status = false;
494 return *tn->stat;
497 if (tn->buf.data_index < tn->buf.data_len)
498 return tn->buf.dmabuf[tn->buf.data_index++];
500 dev_err(tn->dev, "No data to read, idx: 0x%x, len: 0x%x\n",
501 tn->buf.data_index, tn->buf.data_len);
513 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
515 if (len > tn->buf.data_len - tn->buf.data_index) {
516 dev_err(tn->dev, "Not enough data for read of %d bytes\n", len);
520 memcpy(buf, tn->buf.dmabuf + tn->buf.data_index, len);
521 tn->buf.data_index += len;
528 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
530 memcpy(tn->buf.dmabuf + tn->buf.data_len, buf, len);
531 tn->buf.data_len += len;
593 static int set_default_timings(struct octeontx_nfc *tn,
605 /*struct octeontx_nfc *tn = to_otx_nfc(chip->nand.controller);*/
613 static int ndf_cmd_queue_free(struct octeontx_nfc *tn)
617 ndf_misc = readq(tn->base + NDF_MISC);
622 static int ndf_submit(struct octeontx_nfc *tn, union ndf_cmd *cmd)
637 if (ndf_cmd_queue_free(tn) < 8)
639 writeq(cmd->val[0], tn->base + NDF_CMD);
644 if (ndf_cmd_queue_free(tn) < 8)
646 writeq(cmd->val[0], tn->base + NDF_CMD);
648 if (ndf_cmd_queue_free(tn) < 16)
650 writeq(cmd->val[0], tn->base + NDF_CMD);
651 writeq(cmd->val[1], tn->base + NDF_CMD);
655 if (ndf_cmd_queue_free(tn) < 16)
657 writeq(cmd->val[0], tn->base + NDF_CMD);
658 writeq(cmd->val[1], tn->base + NDF_CMD);
661 dev_err(tn->dev, "%s: unknown command: %u\n", __func__, opcode);
667 dev_err(tn->dev, "%s: no space left in command queue\n", __func__);
675 static int ndf_build_wait_busy(struct octeontx_nfc *tn)
684 if (ndf_submit(tn, &cmd))
689 static bool ndf_dma_done(struct octeontx_nfc *tn)
694 dma_cfg = readq(tn->base + NDF_DMA_CFG);
701 static int ndf_wait(struct octeontx_nfc *tn)
706 while (!(done = ndf_dma_done(tn)) && get_timer(start) < NDF_TIMEOUT)
710 dev_err(tn->dev, "%s: timeout error\n", __func__);
716 static int ndf_wait_idle(struct octeontx_nfc *tn)
724 rc = readq_poll_timeout(tn->base + NDF_ST_REG,
727 rc = readq_poll_timeout(tn->base + NDF_DMA_CFG,
735 static int ndf_queue_cmd_timing(struct octeontx_nfc *tn,
750 return ndf_submit(tn, &cmd);
754 static int ndf_queue_cmd_bus(struct octeontx_nfc *tn, int direction)
761 return ndf_submit(tn, &cmd);
765 static int ndf_queue_cmd_chip(struct octeontx_nfc *tn, int enable, int chip,
775 return ndf_submit(tn, &cmd);
778 static int ndf_queue_cmd_wait(struct octeontx_nfc *tn, int t_delay)
785 return ndf_submit(tn, &cmd);
788 static int ndf_queue_cmd_cle(struct octeontx_nfc *tn, int command)
798 return ndf_submit(tn, &cmd);
801 static int ndf_queue_cmd_ale(struct octeontx_nfc *tn, int addr_bytes,
856 return ndf_submit(tn, &cmd);
859 static int ndf_queue_cmd_write(struct octeontx_nfc *tn, int len)
868 return ndf_submit(tn, &cmd);
871 static int ndf_build_pre_cmd(struct octeontx_nfc *tn, int cmd1,
874 struct nand_chip *nand = tn->controller.active;
893 rc = ndf_queue_cmd_timing(tn, timings);
897 rc = ndf_queue_cmd_bus(tn, NDF_BUS_ACQUIRE);
901 rc = ndf_queue_cmd_chip(tn, 1, tn->selected_chip, width);
905 rc = ndf_queue_cmd_wait(tn, t1);
909 rc = ndf_queue_cmd_cle(tn, cmd1);
914 rc = ndf_build_wait_busy(tn);
918 rc = ndf_queue_cmd_ale(tn, addr_bytes, nand,
926 rc = ndf_build_wait_busy(tn);
930 rc = ndf_queue_cmd_cle(tn, cmd2);
937 static int ndf_build_post_cmd(struct octeontx_nfc *tn, int hold_time)
942 rc = ndf_queue_cmd_chip(tn, 0, 0, 0);
946 rc = ndf_queue_cmd_wait(tn, t2);
951 rc = ndf_queue_cmd_bus(tn, 0);
955 rc = ndf_queue_cmd_wait(tn, hold_time);
963 writeq(1, tn->base + NDF_DRBELL);
968 static void ndf_setup_dma(struct octeontx_nfc *tn, int is_write,
976 writeq(bus_addr, tn->base + NDF_DMA_ADR);
977 writeq(dma_cfg, tn->base + NDF_DMA_CFG);
980 static int octeontx_nand_reset(struct octeontx_nfc *tn)
984 rc = ndf_build_pre_cmd(tn, NAND_CMD_RESET, 0, 0, 0, 0);
988 rc = ndf_build_wait_busy(tn);
992 rc = ndf_build_post_cmd(tn, t2);
999 static int ndf_read(struct octeontx_nfc *tn, int cmd1, int addr_bytes,
1002 dma_addr_t bus_addr = tn->use_status ? tn->stat_addr : tn->buf.dmaaddr;
1003 struct nand_chip *nand = tn->controller.active;
1009 tn, cmd1, addr_bytes, page, col, cmd2, len);
1016 rc = ndf_build_pre_cmd(tn, cmd1, addr_bytes, page, col, cmd2);
1018 dev_err(tn->dev, "Build pre command failed\n");
1023 rc = ndf_build_wait_busy(tn);
1025 dev_err(tn->dev, "Wait timeout\n");
1041 rc = ndf_submit(tn, &cmd);
1043 dev_err(tn->dev, "Error submitting command\n");
1048 ndf_setup_dma(tn, 0, bus_addr, len);
1050 rc = ndf_build_post_cmd(tn, t2);
1052 dev_err(tn->dev, "Build post command failed\n");
1057 rc = ndf_wait(tn);
1059 dev_err(tn->dev, "DMA timed out\n");
1063 end = readq(tn->base + NDF_DMA_ADR);
1067 rc = ndf_wait_idle(tn);
1069 dev_err(tn->dev, "poll idle failed\n");
1082 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1087 memset(tn->buf.dmabuf, 0xff, len);
1088 tn->buf.data_index = 0;
1089 tn->buf.data_len = 0;
1090 rc = ndf_read(tn, NAND_CMD_GET_FEATURES, 1, feature_addr, 0, 0, len);
1094 memcpy(subfeature_para, tn->buf.dmabuf, ONFI_SUBFEATURE_PARAM_LEN);
1104 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1108 rc = ndf_build_pre_cmd(tn, NAND_CMD_SET_FEATURES,
1113 memcpy(tn->buf.dmabuf, subfeature_para, len);
1114 memset(tn->buf.dmabuf + len, 0, 8 - len);
1116 ndf_setup_dma(tn, 1, tn->buf.dmaaddr, 8);
1118 rc = ndf_queue_cmd_write(tn, 8);
1122 rc = ndf_build_wait_busy(tn);
1126 rc = ndf_build_post_cmd(tn, t2);
1137 static int ndf_page_read(struct octeontx_nfc *tn, u64 page, int col, int len)
1140 tn, page, col, len, tn->controller.active);
1141 struct nand_chip *nand = tn->controller.active;
1145 memset(tn->buf.dmabuf, 0xff, len);
1146 return ndf_read(tn, NAND_CMD_READ0, addr_bytes,
1151 static int ndf_block_erase(struct octeontx_nfc *tn, u64 page_addr)
1153 struct nand_chip *nand = tn->controller.active;
1158 rc = ndf_build_pre_cmd(tn, NAND_CMD_ERASE1, addr_bytes,
1164 rc = ndf_build_wait_busy(tn);
1168 rc = ndf_build_post_cmd(tn, t2);
1173 return ndf_wait_idle(tn);
1179 static int ndf_page_write(struct octeontx_nfc *tn, int page)
1182 struct nand_chip *nand = tn->controller.active;
1186 len = tn->buf.data_len - tn->buf.data_index;
1187 chip->oob_only = (tn->buf.data_index >= nand->mtd.writesize);
1190 ndf_setup_dma(tn, 1, tn->buf.dmaaddr + tn->buf.data_index, len);
1191 rc = ndf_build_pre_cmd(tn, NAND_CMD_SEQIN, addr_bytes, page, 0, 0);
1195 rc = ndf_queue_cmd_write(tn, len);
1199 rc = ndf_queue_cmd_cle(tn, NAND_CMD_PAGEPROG);
1204 rc = ndf_build_wait_busy(tn);
1208 rc = ndf_build_post_cmd(tn, t2);
1213 rc = ndf_wait(tn);
1218 return ndf_wait_idle(tn);
1226 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1229 tn->selected_chip = octeontx_nand->cs;
1230 if (tn->selected_chip < 0 || tn->selected_chip >= NAND_MAX_CHIPS) {
1231 dev_err(tn->dev, "invalid chip select\n");
1235 tn->use_status = false;
1238 column, page_addr, tn->selected_chip);
1241 tn->buf.data_index = 0;
1243 rc = ndf_read(tn, command, 1, column, 0, 0, 8);
1245 dev_err(tn->dev, "READID failed with %d\n", rc);
1247 tn->buf.data_len = rc;
1252 tn->buf.data_index = 0;
1253 tn->buf.data_len = 0;
1254 rc = ndf_page_read(tn, page_addr, column, mtd->oobsize);
1256 dev_err(tn->dev, "READOOB failed with %d\n",
1257 tn->buf.data_len);
1259 tn->buf.data_len = rc;
1264 tn->buf.data_index = 0;
1265 tn->buf.data_len = 0;
1266 rc = ndf_page_read(tn, page_addr, column,
1270 dev_err(tn->dev, "READ0 failed with %d\n", rc);
1272 tn->buf.data_len = rc;
1277 tn->use_status = true;
1278 rc = ndf_read(tn, command, 0, 0, 0, 0, 8);
1280 dev_err(tn->dev, "STATUS failed with %d\n", rc);
1285 rc = octeontx_nand_reset(tn);
1287 dev_err(tn->dev, "RESET failed with %d\n", rc);
1292 tn->buf.data_index = 0;
1293 rc = ndf_read(tn, command, 1, 0, 0, 0,
1294 min(tn->buf.dmabuflen, 3 * 512));
1296 dev_err(tn->dev, "PARAM failed with %d\n", rc);
1298 tn->buf.data_len = rc;
1302 tn->buf.data_index = column;
1306 if (ndf_block_erase(tn, page_addr))
1307 dev_err(tn->dev, "ERASE1 failed\n");
1318 tn->buf.data_index = column;
1319 tn->buf.data_len = column;
1325 rc = ndf_page_write(tn, octeontx_nand->selected_page);
1327 dev_err(tn->dev, "PAGEPROG failed with %d\n", rc);
1332 /* assume tn->buf.data_len == 4 of data has been set there */
1334 page_addr, tn->buf.dmabuf);
1336 dev_err(tn->dev, "SET_FEATURES failed with %d\n", rc);
1342 page_addr, tn->buf.dmabuf);
1344 tn->buf.data_index = 0;
1345 tn->buf.data_len = 4;
1347 dev_err(tn->dev, "GET_FEATURES failed with %d\n", rc);
1353 dev_err(tn->dev, "unhandled nand cmd: %x\n", command);
1359 struct octeontx_nfc *tn = to_otx_nfc(chip->controller);
1362 ret = ndf_wait_idle(tn);
1442 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1448 union bch_resp *r = tn->bch_resp;
1463 (dma_addr_t)ecc_handle, tn->bch_rhandle);
1466 octeontx_bch_wait(bch_vf, r, tn->bch_rhandle);
1468 dev_err(tn->dev, "octeontx_bch_encode failed\n");
1473 dev_err(tn->dev,
1484 code[i] ^= tn->eccmask[i];
1486 return tn->bch_resp->s.num_errors;
1524 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1530 union bch_resp *r = tn->bch_resp;
1539 dev_err(tn->dev,
1551 data_buffer[nand->ecc.size + i] ^= tn->eccmask[i];
1558 nand->ecc.strength, ohandle, tn->bch_rhandle);
1561 octeontx_bch_wait(bch_vf, r, tn->bch_rhandle);
1564 dev_err(tn->dev, "octeontx_bch_decode failed\n");
1569 dev_err(tn->dev, "Error: BCH engine timeout\n");
1602 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1611 memcpy(chip->oob_poi, tn->buf.dmabuf + mtd->writesize, mtd->oobsize);
1614 p = tn->buf.dmabuf;
1638 memcpy(buf, tn->buf.dmabuf, mtd->writesize);
1648 struct octeontx_nfc *tn = to_otx_nfc(chip->controller);
1663 p = tn->buf.dmabuf;
1770 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1797 if (!tn->eccmask)
1798 tn->eccmask = devm_kzalloc(tn->dev, ecc->bytes, GFP_KERNEL);
1799 if (!tn->eccmask)
1811 struct octeontx_nfc *tn = to_otx_nfc(nand->controller);
1834 tn->eccmask[i] = erased_ecc[i] ^ 0xff;
1890 struct octeontx_nfc *tn =
1910 tn->selected_chip);
1922 static int octeontx_nfc_chip_init(struct octeontx_nfc *tn, struct udevice *dev,
1947 nand->controller = &tn->controller;
1948 if (!tn->controller.active)
1949 tn->controller.active = nand;
1970 readq(tn->base + NDF_MISC));
1992 list_add_tail(&chip->node, &tn->chips);
1996 static int octeontx_nfc_chips_init(struct octeontx_nfc *tn)
1998 struct udevice *dev = tn->dev;
2020 __func__, tn, dev->name, nand_node.of_offset);
2021 ret = octeontx_nfc_chip_init(tn, dev, nand_node);
2029 static int octeontx_nfc_init(struct octeontx_nfc *tn)
2036 ndf_misc = readq(tn->base + NDF_MISC);
2040 writeq(ndf_misc, tn->base + NDF_MISC);
2041 debug("%s: NDF_MISC: 0x%llx\n", __func__, readq(tn->base + NDF_MISC));
2049 writeq(ndf_misc, tn->base + NDF_MISC);
2055 rc = set_default_timings(tn, timings);
2064 struct octeontx_nfc *tn = dev_get_priv(dev);
2068 debug("%s(%s) tn: %p\n", __func__, dev->name, tn);
2093 tn->dev = dev;
2094 INIT_LIST_HEAD(&tn->chips);
2096 tn->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM);
2097 if (!tn->base) {
2101 debug("%s: bar at %p\n", __func__, tn->base);
2102 tn->buf.dmabuflen = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
2103 tn->buf.dmabuf = dma_alloc_coherent(tn->buf.dmabuflen,
2104 (unsigned long *)&tn->buf.dmaaddr);
2105 if (!tn->buf.dmabuf) {
2112 tn->bch_resp = dma_alloc_coherent(sizeof(*tn->bch_resp),
2113 (unsigned long *)&tn->bch_rhandle);
2115 tn->stat = dma_alloc_coherent(8, (unsigned long *)&tn->stat_addr);
2116 if (!tn->stat || !tn->bch_resp) {
2124 octeontx_nfc_init(tn);
2126 ret = octeontx_nfc_chips_init(tn);
2143 struct octeontx_nfc *tn = dev_get_priv(dev);
2148 dma_cfg = readq(tn->base + NDF_DMA_CFG);
2151 writeq(dma_cfg, tn->base + NDF_DMA_CFG);
2154 ndf_misc = readq(tn->base + NDF_MISC);
2156 writeq(ndf_misc, tn->base + NDF_MISC);
2158 writeq(ndf_misc, tn->base + NDF_MISC);
2160 printf("%s: NDF_MISC: 0x%llx\n", __func__, readq(tn->base + NDF_MISC));
2163 writeq(~0ull, tn->base + NDF_INT_ENA_W1C);
2164 writeq(~0ull, tn->base + NDF_INT);
2166 readq(tn->base + NDF_ST_REG));