nand/raw/lpc32xx_nand_mlc.c

192 	int status = readl(&lpc32xx_nand_mlc_registers->isr);
193 	return status & ISR_CONTROLLER_READY;
240 	unsigned int i, status, timeout, err, max_bitflips = 0;
249 			status = readl(&lpc32xx_nand_mlc_registers->isr);
250 			if (status & ISR_CONTROLLER_READY)
255 		if (status & ISR_DECODER_FAILURE)
258 		if (status & ISR_DECODER_ERROR) {
259 			err = ISR_DECODER_ERRORS(status);
288 	unsigned int i, status, timeout;
297 			status = readl(&lpc32xx_nand_mlc_registers->isr);
298 			if (status & ISR_NAND_READY)
303 		if (!(status & ISR_NAND_READY))
336 	unsigned int i, status, timeout, err, max_bitflips = 0;
349 			status = readl(&lpc32xx_nand_mlc_registers->isr);
350 			if (status & ISR_CONTROLLER_READY)
355 		if (status & ISR_DECODER_FAILURE)
358 		if (status & ISR_DECODER_ERROR) {
359 			err = ISR_DECODER_ERRORS(status);
390 	unsigned int i, status, timeout;
403 			status = readl(&lpc32xx_nand_mlc_registers->isr);
404 			if (status & ISR_ECC_READY)
409 		if (!(status & ISR_ECC_READY))
415 			status = readl(&lpc32xx_nand_mlc_registers->isr);
416 			if (status & ISR_CONTROLLER_READY)
421 		if (!(status & ISR_CONTROLLER_READY))
484 	unsigned int i, status, timeout;
496 			status = readl(&lpc32xx_nand_mlc_registers->isr);
497 			if (status & ISR_NAND_READY)
502 		if (!(status & ISR_NAND_READY))
518 	int status;
522 		status = readl(&lpc32xx_nand_mlc_registers->isr);
523 		if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
529 	if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
532 	/* write NAND status command */
534 	/* read back status and return it */
627 	int status, i, timeout, err, max_bitflips = 0;
646 			status = readl(&lpc32xx_nand_mlc_registers->isr);
647 			if (status & ISR_CONTROLLER_READY)
652 		if (!(status & ISR_CONTROLLER_READY))
655 		if (status & ISR_DECODER_FAILURE)
658 		if (status & ISR_DECODER_ERROR) {
659 			err = ISR_DECODER_ERRORS(status);