drivers/mmc/sh_mmcif.c

31 	struct sh_mmcif_host *host = dev_id;
34 	state = sh_mmcif_read(&host->regs->ce_int);
35 	state &= sh_mmcif_read(&host->regs->ce_int_mask);
38 		sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
39 		sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
42 		sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
43 		sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
45 		if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
49 		sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
50 		sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
53 		sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
54 		sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
58 				  INT_BUFRE), &host->regs->ce_int);
59 		sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
62 		sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
63 		sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
66 		sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
67 		sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
71 				&host->regs->ce_int);
72 		sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
76 		sh_mmcif_write(~state, &host->regs->ce_int);
77 		sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
83 	host->sd_error = 1;
86 	host->wait_int = 1;
90 static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
101 		if (!sh_mmcif_intr(host))
110 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
112 	sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
113 	sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
119 		sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
121 		sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
123 				&host->regs->ce_clk_ctrl);
124 	sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
127 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
131 	tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
134 	sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
135 	sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
137 			&host->regs->ce_clk_ctrl);
139 	sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
142 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
147 	host->sd_error = 0;
148 	host->wait_int = 0;
150 	state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
151 	state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
153 			DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
155 			DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
159 		sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
160 		sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
168 			if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
172 		sh_mmcif_sync_reset(host);
185 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
197 	host->wait_int = 0;
200 	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
201 	time = mmcif_wait_interrupt_flag(host);
202 	if (time == 0 || host->sd_error != 0)
203 		return sh_mmcif_error_manage(host);
205 	host->wait_int = 0;
207 			sh_mmcif_read(&host->regs->ce_block_set)) + 3;
209 		*p++ = sh_mmcif_read(&host->regs->ce_data);
212 	sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
213 	time = mmcif_wait_interrupt_flag(host);
214 	if (time == 0 || host->sd_error != 0)
215 		return sh_mmcif_error_manage(host);
217 	host->wait_int = 0;
221 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
233 	host->wait_int = 0;
234 	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
236 		sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
237 		time = mmcif_wait_interrupt_flag(host);
238 		if (time == 0 || host->sd_error != 0)
239 			return sh_mmcif_error_manage(host);
241 		host->wait_int = 0;
243 			*p++ = sh_mmcif_read(&host->regs->ce_data);
250 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
262 	host->wait_int = 0;
263 	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
265 	time = mmcif_wait_interrupt_flag(host);
266 	if (time == 0 || host->sd_error != 0)
267 		return sh_mmcif_error_manage(host);
269 	host->wait_int = 0;
271 			sh_mmcif_read(&host->regs->ce_block_set)) + 3;
273 		sh_mmcif_write(*p++, &host->regs->ce_data);
276 	sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
278 	time = mmcif_wait_interrupt_flag(host);
279 	if (time == 0 || host->sd_error != 0)
280 		return sh_mmcif_error_manage(host);
282 	host->wait_int = 0;
286 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
298 	host->wait_int = 0;
299 	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
301 		sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
303 		time = mmcif_wait_interrupt_flag(host);
305 		if (time == 0 || host->sd_error != 0)
306 			return sh_mmcif_error_manage(host);
308 		host->wait_int = 0;
310 			sh_mmcif_write(*p++, &host->regs->ce_data);
317 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
321 		cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
322 		cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
323 		cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
324 		cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
328 		cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
332 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
335 	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
338 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
367 	if (host->data) {
369 		switch (host->bus_width) {
392 		sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
409 static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
416 		ret = sh_mmcif_multi_read(host, data);
419 		ret = sh_mmcif_multi_write(host, data);
422 		ret = sh_mmcif_single_write(host, data);
426 		ret = sh_mmcif_single_read(host, data);
436 static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
445 		if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
447 					&host->regs->ce_int_mask);
450 					&host->regs->ce_int_mask);
452 		time = mmcif_wait_interrupt_flag(host);
453 		if (time == 0 || host->sd_error != 0)
454 			return sh_mmcif_error_manage(host);
456 		sh_mmcif_get_cmd12response(host, cmd);
469 	if (host->data) {
470 		sh_mmcif_write(0, &host->regs->ce_block_set);
471 		sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
473 	opc = sh_mmcif_set_cmd(host, data, cmd);
475 	sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
476 	sh_mmcif_write(mask, &host->regs->ce_int_mask);
480 	sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
481 	host->wait_int = 0;
483 	sh_mmcif_write(opc, &host->regs->ce_cmd_set);
485 	time = mmcif_wait_interrupt_flag(host);
487 		return sh_mmcif_error_manage(host);
489 	if (host->sd_error) {
498 			ret = sh_mmcif_error_manage(host);
501 		host->sd_error = 0;
502 		host->wait_int = 0;
510 	if (host->wait_int == 1) {
511 		sh_mmcif_get_response(host, cmd);
512 		host->wait_int = 0;
514 	if (host->data)
515 		ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
516 	host->last_cmd = cmd->cmdidx;
521 static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
541 	host->sd_error = 0;
542 	host->data = data;
543 	ret = sh_mmcif_start_cmd(host, data, cmd);
544 	host->data = NULL;
549 static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
552 		sh_mmcif_clock_control(host, mmc->clock);
555 		host->bus_width = MMC_BUS_WIDTH_8;
557 		host->bus_width = MMC_BUS_WIDTH_4;
559 		host->bus_width = MMC_BUS_WIDTH_1;
566 static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
568 	sh_mmcif_sync_reset(host);
569 	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
582 	struct sh_mmcif_host *host = mmc_priv(mmc);
584 	return sh_mmcif_send_cmd_common(host, cmd, data);
589 	struct sh_mmcif_host *host = mmc_priv(mmc);
591 	return sh_mmcif_set_ios_common(host, mmc);
596 	struct sh_mmcif_host *host = mmc_priv(mmc);
598 	return sh_mmcif_initialize_common(host);
619 	struct sh_mmcif_host *host = NULL;
621 	host = malloc(sizeof(struct sh_mmcif_host));
622 	if (!host)
624 	memset(host, 0, sizeof(*host));
626 	host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
627 	host->clk = CONFIG_SH_MMCIF_CLK;
629 	sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
630 	sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
632 	mmc = mmc_create(&sh_mmcif_cfg, host);
634 		free(host);
650 	struct sh_mmcif_host *host = dev_get_priv(dev);
652 	return sh_mmcif_send_cmd_common(host, cmd, data);
657 	struct sh_mmcif_host *host = dev_get_priv(dev);
660 	return sh_mmcif_set_ios_common(host, mmc);
678 	struct sh_mmcif_host *host = dev_get_priv(dev);
688 	host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
689 	if (!host->regs)
704 	host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
724 	sh_mmcif_initialize_common(host);
727 	plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
728 	plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);