Lines Matching refs:host
404 static void msdc_reset_hw(struct msdc_host *host)
408 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
410 readl_poll_timeout(&host->base->msdc_cfg, reg,
414 static void msdc_fifo_clr(struct msdc_host *host)
418 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
420 readl_poll_timeout(&host->base->msdc_fifocs, reg,
424 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
426 return (readl(&host->base->msdc_fifocs) &
430 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
432 return (readl(&host->base->msdc_fifocs) &
436 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
463 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
468 u32 resp_type = msdc_cmd_find_resp(host, cmd);
513 static int msdc_cmd_done(struct msdc_host *host, int events,
521 rsp[0] = readl(&host->base->sdc_resp[3]);
522 rsp[1] = readl(&host->base->sdc_resp[2]);
523 rsp[2] = readl(&host->base->sdc_resp[1]);
524 rsp[3] = readl(&host->base->sdc_resp[0]);
526 rsp[0] = readl(&host->base->sdc_resp[0]);
537 msdc_reset_hw(host);
548 static bool msdc_cmd_is_ready(struct msdc_host *host)
554 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
559 msdc_reset_hw(host);
563 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
564 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
569 msdc_reset_hw(host);
577 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
585 if (!msdc_cmd_is_ready(host))
588 if ((readl(&host->base->msdc_fifocs) &
590 (readl(&host->base->msdc_fifocs) &
593 msdc_reset_hw(host);
596 msdc_fifo_clr(host);
598 host->last_resp_type = cmd->resp_type;
599 host->last_data_write = 0;
601 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
606 writel(CMD_INTS_MASK, &host->base->msdc_int);
607 writel(DATA_INTS_MASK, &host->base->msdc_int);
608 writel(blocks, &host->base->sdc_blk_num);
609 writel(cmd->cmdarg, &host->base->sdc_arg);
610 writel(rawcmd, &host->base->sdc_cmd);
612 ret = readl_poll_timeout(&host->base->msdc_int, status,
618 return msdc_cmd_done(host, status, cmd);
621 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
626 *buf++ = readb(&host->base->msdc_rxdata);
632 *wbuf++ = readl(&host->base->msdc_rxdata);
638 *buf++ = readb(&host->base->msdc_rxdata);
643 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
648 writeb(*buf++, &host->base->msdc_txdata);
654 writel(*wbuf++, &host->base->msdc_txdata);
660 writeb(*buf++, &host->base->msdc_txdata);
665 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
672 status = readl(&host->base->msdc_int);
673 writel(status, &host->base->msdc_int);
688 if (msdc_fifo_rx_bytes(host) >= chksz) {
689 msdc_fifo_read(host, ptr, chksz);
707 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
714 status = readl(&host->base->msdc_int);
715 writel(status, &host->base->msdc_int);
739 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
740 msdc_fifo_write(host, ptr, chksz);
749 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
755 host->last_data_write = 1;
760 ret = msdc_pio_write(host, (const u8 *)data->src, size);
762 ret = msdc_pio_read(host, (u8 *)data->dest, size);
765 msdc_reset_hw(host);
766 msdc_fifo_clr(host);
775 struct msdc_host *host = dev_get_priv(dev);
778 cmd_ret = msdc_start_command(host, cmd, data);
786 data_ret = msdc_start_data(host, data);
796 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
801 host->timeout_ns = ns;
802 host->timeout_clks = clks;
804 if (host->sclk == 0) {
807 clk_ns = 1000000000UL / host->sclk;
811 if (host->dev_comp->clk_div_bits == 8)
812 mode = (readl(&host->base->msdc_cfg) &
815 mode = (readl(&host->base->msdc_cfg) &
823 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
827 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
829 u32 val = readl(&host->base->sdc_cfg);
846 writel(val, &host->base->sdc_cfg);
850 struct msdc_host *host, enum bus_mode timing, u32 hz)
858 host->mclk = 0;
859 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
863 if (host->dev_comp->clk_div_bits == 8)
864 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
866 clrbits_le32(&host->base->msdc_cfg,
876 if (hz >= (host->src_clk_freq >> 2)) {
878 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
880 div = (host->src_clk_freq + ((hz << 2) - 1)) /
882 sclk = (host->src_clk_freq >> 2) / div;
886 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
887 if (host->dev_comp->clk_div_bits == 8)
888 setbits_le32(&host->base->msdc_cfg,
891 setbits_le32(&host->base->msdc_cfg,
894 sclk = host->src_clk_freq >> 1;
897 } else if (hz >= host->src_clk_freq) {
900 sclk = host->src_clk_freq;
903 if (hz >= (host->src_clk_freq >> 1)) {
905 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
907 div = (host->src_clk_freq + ((hz << 2) - 1)) /
909 sclk = (host->src_clk_freq >> 2) / div;
913 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
915 if (host->dev_comp->clk_div_bits == 8) {
917 clrsetbits_le32(&host->base->msdc_cfg,
924 clrsetbits_le32(&host->base->msdc_cfg,
930 readl_poll_timeout(&host->base->msdc_cfg, reg,
933 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
934 host->sclk = sclk;
935 host->mclk = hz;
936 host->timing = timing;
939 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
945 if (host->sclk <= 52000000) {
946 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
947 writel(host->def_tune_para.pad_tune,
948 &host->base->pad_tune);
950 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
951 writel(host->saved_tune_para.pad_tune,
952 &host->base->pad_tune);
955 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
961 struct msdc_host *host = dev_get_priv(dev);
965 msdc_set_buswidth(host, mmc->bus_width);
972 if (host->mclk != clock || host->timing != mmc->selected_mode)
973 msdc_set_mclk(dev, host, mmc->selected_mode, clock);
980 struct msdc_host *host = dev_get_priv(dev);
983 if (host->builtin_cd) {
984 val = readl(&host->base->msdc_ps);
987 return !val ^ host->cd_active_high;
991 if (!host->gpio_cd.dev)
994 return dm_gpio_get_value(&host->gpio_cd);
1003 struct msdc_host *host = dev_get_priv(dev);
1005 if (!host->gpio_wp.dev)
1008 return !dm_gpio_get_value(&host->gpio_wp);
1034 struct msdc_host *host, u32 delay)
1074 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1076 void __iomem *tune_reg = &host->base->pad_tune;
1078 if (host->dev_comp->pad_tune0)
1079 tune_reg = &host->base->pad_tune0;
1081 if (host->top_base)
1082 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
1089 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1091 void __iomem *tune_reg = &host->base->pad_tune;
1093 if (host->dev_comp->pad_tune0)
1094 tune_reg = &host->base->pad_tune0;
1096 if (host->top_base)
1097 clrsetbits_le32(&host->top_base->emmc_top_control,
1107 struct msdc_host *host = dev_get_priv(dev);
1112 void __iomem *tune_reg = &host->base->pad_cmd_tune;
1116 setbits_le32(&host->base->pad_cmd_tune, BIT(0));
1121 host->hs200_cmd_int_delay <<
1124 if (host->r_smpl)
1125 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1127 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1144 final_cmd_delay = get_best_delay(dev, host, cmd_delay);
1157 struct msdc_host *host = dev_get_priv(dev);
1164 void __iomem *tune_reg = &host->base->pad_tune;
1168 if (host->dev_comp->pad_tune0)
1169 tune_reg = &host->base->pad_tune0;
1174 host->hs200_cmd_int_delay <<
1177 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1194 final_rise_delay = get_best_delay(dev, host, rise_delay);
1200 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1216 final_fall_delay = get_best_delay(dev, host, fall_delay);
1221 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1227 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1234 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1248 internal_delay_phase = get_best_delay(dev, host, internal_delay);
1261 struct msdc_host *host = dev_get_priv(dev);
1266 void __iomem *tune_reg = &host->base->pad_tune;
1269 if (host->dev_comp->pad_tune0)
1270 tune_reg = &host->base->pad_tune0;
1272 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1273 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1290 final_rise_delay = get_best_delay(dev, host, rise_delay);
1295 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1296 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1313 final_fall_delay = get_best_delay(dev, host, fall_delay);
1318 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1319 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1325 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1326 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1336 host->hs200_write_int_delay <<
1351 struct msdc_host *host = dev_get_priv(dev);
1358 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1359 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1362 msdc_set_cmd_delay(host, i);
1363 msdc_set_data_delay(host, i);
1369 final_rise_delay = get_best_delay(dev, host, rise_delay);
1374 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1375 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1378 msdc_set_cmd_delay(host, i);
1379 msdc_set_data_delay(host, i);
1385 final_fall_delay = get_best_delay(dev, host, fall_delay);
1390 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1391 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1394 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1395 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1399 msdc_set_cmd_delay(host, final_delay);
1400 msdc_set_data_delay(host, final_delay);
1409 struct msdc_host *host = dev_get_priv(dev);
1413 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1421 clrbits_le32(&host->base->msdc_iocon,
1423 clrsetbits_le32(&host->base->pad_tune,
1426 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1428 clrbits_le32(&host->base->patch_bit2,
1430 host->hs400_mode = true;
1453 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1454 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1455 host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
1461 static void msdc_init_hw(struct msdc_host *host)
1464 void __iomem *tune_reg = &host->base->pad_tune;
1465 void __iomem *rd_dly0_reg = &host->base->pad_tune0;
1466 void __iomem *rd_dly1_reg = &host->base->pad_tune1;
1468 if (host->dev_comp->pad_tune0) {
1469 tune_reg = &host->base->pad_tune0;
1470 rd_dly0_reg = &host->base->dat_rd_dly[0];
1471 rd_dly1_reg = &host->base->dat_rd_dly[1];
1475 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1478 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1481 msdc_reset_hw(host);
1484 if (host->builtin_cd)
1485 clrsetbits_le32(&host->base->msdc_ps,
1490 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1493 val = readl(&host->base->msdc_int);
1494 writel(val, &host->base->msdc_int);
1497 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1499 if (host->top_base) {
1500 writel(0, &host->top_base->emmc_top_control);
1501 writel(0, &host->top_base->emmc_top_cmd);
1505 writel(0, &host->base->msdc_iocon);
1507 if (host->r_smpl)
1508 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1510 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1512 writel(0x403c0046, &host->base->patch_bit0);
1513 writel(0xffff4089, &host->base->patch_bit1);
1515 if (host->dev_comp->stop_clk_fix) {
1516 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1518 clrbits_le32(&host->base->sdc_fifo_cfg,
1520 clrbits_le32(&host->base->sdc_fifo_cfg,
1524 if (host->dev_comp->busy_check)
1525 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1527 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1529 if (host->dev_comp->async_fifo) {
1530 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1533 if (host->dev_comp->enhance_rx) {
1534 if (host->top_base)
1535 setbits_le32(&host->top_base->emmc_top_control,
1538 setbits_le32(&host->base->sdc_adv_cfg0,
1541 clrsetbits_le32(&host->base->patch_bit2,
1544 clrsetbits_le32(&host->base->patch_bit2,
1550 clrbits_le32(&host->base->patch_bit2,
1552 clrbits_le32(&host->base->patch_bit2,
1556 if (host->dev_comp->data_tune) {
1557 if (host->top_base) {
1558 setbits_le32(&host->top_base->emmc_top_control,
1560 clrbits_le32(&host->top_base->emmc_top_control,
1562 setbits_le32(&host->top_base->emmc_top_cmd,
1567 clrsetbits_le32(&host->base->patch_bit0,
1569 host->latch_ck <<
1574 if (host->top_base)
1575 setbits_le32(&host->top_base->emmc_top_control,
1581 if (host->dev_comp->builtin_pad_ctrl) {
1585 (4 << MSDC_PAD_CTRL0_CLKDRVP_S), &host->base->pad_ctrl0);
1588 (4 << MSDC_PAD_CTRL1_CMDDRVP_S), &host->base->pad_ctrl1);
1591 (4 << MSDC_PAD_CTRL2_DATDRVP_S), &host->base->pad_ctrl2);
1594 if (host->dev_comp->default_pad_dly) {
1621 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1624 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1627 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1631 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1632 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1635 static void msdc_ungate_clock(struct msdc_host *host)
1637 clk_enable(&host->src_clk);
1638 clk_enable(&host->h_clk);
1639 if (host->src_clk_cg.dev)
1640 clk_enable(&host->src_clk_cg);
1647 struct msdc_host *host = dev_get_priv(dev);
1652 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1654 host->src_clk_freq = clk_get_rate(&host->src_clk);
1656 if (host->dev_comp->clk_div_bits == 8)
1657 cfg->f_min = host->src_clk_freq / (4 * 255);
1659 cfg->f_min = host->src_clk_freq / (4 * 4095);
1664 if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq)
1665 cfg->f_max = host->src_clk_freq;
1670 host->mmc = &plat->mmc;
1671 host->timeout_ns = 100000000;
1672 host->timeout_clks = 3 * (1 << SCLK_CYCLES_SHIFT);
1678 msdc_ungate_clock(host);
1679 msdc_init_hw(host);
1689 struct msdc_host *host = dev_get_priv(dev);
1697 host->base = map_sysmem(base, 0);
1701 host->top_base = NULL;
1703 host->top_base = map_sysmem(top_base, 0);
1709 ret = clk_get_by_name(dev, "source", &host->src_clk);
1713 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1717 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1720 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1721 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1724 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1725 host->hs200_cmd_int_delay =
1727 host->hs200_write_int_delay =
1729 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1730 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1731 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1732 host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1746 struct msdc_host *host = dev_get_priv(dev);
1750 ret = readl_poll_sleep_timeout(&host->base->msdc_ps, reg,