drivers/mmc/dw_mmc.c

24 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
29 	dwmci_writel(host, DWMCI_CTRL, value);
32 		ctrl = dwmci_readl(host, DWMCI_CTRL);
50 static void dwmci_prepare_data(struct dwmci_host *host,
62 	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
65 	dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
68 	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
92 	ctrl = dwmci_readl(host, DWMCI_CTRL);
94 	dwmci_writel(host, DWMCI_CTRL, ctrl);
96 	ctrl = dwmci_readl(host, DWMCI_BMOD);
98 	dwmci_writel(host, DWMCI_BMOD, ctrl);
100 	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
101 	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
104 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
108 	*len = dwmci_readl(host, DWMCI_STATUS);
111 		*len = dwmci_readl(host, DWMCI_STATUS);
137 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
139 	struct mmc *mmc = host->mmc;
144 	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
158 		mask = dwmci_readl(host, DWMCI_RINTSTS);
166 		if (host->fifo_mode && size) {
170 				dwmci_writel(host, DWMCI_RINTSTS,
174 					ret = dwmci_fifo_ready(host,
185 						dwmci_readl(host, DWMCI_DATA);
191 					ret = dwmci_fifo_ready(host,
202 						dwmci_writel(host, DWMCI_DATA,
206 				dwmci_writel(host, DWMCI_RINTSTS,
226 	dwmci_writel(host, DWMCI_RINTSTS, mask);
231 static int dwmci_set_transfer_mode(struct dwmci_host *host,
253 	struct dwmci_host *host = mmc->priv;
263 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
270 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
273 		if (host->fifo_mode) {
274 			dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
275 			dwmci_writel(host, DWMCI_BYTCNT,
277 			dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
294 			dwmci_prepare_data(host, data, cur_idmac,
299 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
302 		flags = dwmci_set_transfer_mode(host, data);
325 	dwmci_writel(host, DWMCI_CMD, flags);
328 		mask = dwmci_readl(host, DWMCI_RINTSTS);
331 				dwmci_writel(host, DWMCI_RINTSTS, mask);
364 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
365 			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
366 			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
367 			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
369 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
374 		ret = dwmci_data_transfer(host, data);
377 		if (!host->fifo_mode) {
382 			ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
388 			dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
390 			ctrl = dwmci_readl(host, DWMCI_CTRL);
392 			dwmci_writel(host, DWMCI_CTRL, ctrl);
402 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
408 	if ((freq == host->clock) || (freq == 0))
411 	 * If host->get_mmc_clk isn't defined,
412 	 * then assume that host->bus_hz is source clock value.
413 	 * host->bus_hz should be set by user.
415 	if (host->get_mmc_clk)
416 		sclk = host->get_mmc_clk(host, freq);
417 	else if (host->bus_hz)
418 		sclk = host->bus_hz;
429 	dwmci_writel(host, DWMCI_CLKENA, 0);
430 	dwmci_writel(host, DWMCI_CLKSRC, 0);
432 	dwmci_writel(host, DWMCI_CLKDIV, div);
433 	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
437 		status = dwmci_readl(host, DWMCI_CMD);
444 	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
447 	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
452 		status = dwmci_readl(host, DWMCI_CMD);
459 	host->clock = freq;
472 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
477 	dwmci_setup_bus(host, mmc->clock);
490 	dwmci_writel(host, DWMCI_CTYPE, ctype);
492 	regs = dwmci_readl(host, DWMCI_UHS_REG);
498 	dwmci_writel(host, DWMCI_UHS_REG, regs);
500 	if (host->clksel) {
503 		ret = host->clksel(host);
532 	struct dwmci_host *host = mmc->priv;
534 	if (host->board_init)
535 		host->board_init(host);
537 	dwmci_writel(host, DWMCI_PWREN, 1);
539 	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
545 	dwmci_setup_bus(host, mmc->cfg->f_min);
547 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
548 	dwmci_writel(host, DWMCI_INTMASK, 0);
550 	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
552 	dwmci_writel(host, DWMCI_IDINTEN, 0);
553 	dwmci_writel(host, DWMCI_BMOD, 1);
555 	if (!host->fifoth_val) {
558 		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
560 		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
563 	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
565 	dwmci_writel(host, DWMCI_CLKENA, 0);
566 	dwmci_writel(host, DWMCI_CLKSRC, 0);
568 	if (!host->fifo_mode)
569 		dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
595 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
598 	cfg->name = host->name;
607 	cfg->host_caps = host->caps;
609 	if (host->buswidth == 8) {
627 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
629 	dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
631 	host->mmc = mmc_create(&host->cfg, host);
632 	if (host->mmc == NULL)