Lines Matching defs:i2c
3 * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/projects/i2c)
21 #include <i2c.h>
75 void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
76 u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
87 static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
89 writeb(value, i2c->base + (reg << i2c->reg_shift));
92 static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
94 writew(value, i2c->base + (reg << i2c->reg_shift));
97 static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
99 writel(value, i2c->base + (reg << i2c->reg_shift));
102 static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
104 out_be16(i2c->base + (reg << i2c->reg_shift), value);
107 static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
109 out_be32(i2c->base + (reg << i2c->reg_shift), value);
112 static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
114 return readb(i2c->base + (reg << i2c->reg_shift));
117 static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg)
119 return readw(i2c->base + (reg << i2c->reg_shift));
122 static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg)
124 return readl(i2c->base + (reg << i2c->reg_shift));
127 static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg)
129 return in_be16(i2c->base + (reg << i2c->reg_shift));
132 static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg)
134 return in_be32(i2c->base + (reg << i2c->reg_shift));
137 static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value)
139 i2c->setreg(i2c, reg, value);
142 static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg)
144 return i2c->getreg(i2c, reg);
152 static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat)
154 struct i2c_msg *msg = i2c->msg;
156 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
158 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
164 i2c->state = STATE_ERROR;
165 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
169 if (i2c->state == STATE_START || i2c->state == STATE_WRITE) {
170 i2c->state =
174 i2c->state = STATE_ERROR;
175 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
179 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
183 if (i2c->pos == msg->len) {
184 i2c->nmsgs--;
185 i2c->msg++;
186 i2c->pos = 0;
187 msg = i2c->msg;
189 if (i2c->nmsgs) { /* end? */
194 i2c->state = STATE_START;
196 oc_setreg(i2c, OCI2C_DATA, addr);
197 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
200 i2c->state = (msg->flags & I2C_M_RD)
203 i2c->state = STATE_DONE;
204 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
209 if (i2c->state == STATE_READ) {
210 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ?
213 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
214 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
220 struct ocores_i2c_bus *i2c = dev_id;
221 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
223 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
229 ocores_process(i2c, stat);
236 * @i2c: ocores I2C device instance
247 static int ocores_wait(struct ocores_i2c_bus *i2c,
254 u8 status = oc_getreg(i2c, reg);
270 * @i2c: ocores I2C device instance
276 static int ocores_poll_wait(struct ocores_i2c_bus *i2c)
281 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
291 udelay((8 * 1000) / i2c->bus_clk_khz);
298 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1);
307 * @i2c: ocores I2C device instance
315 static void ocores_process_polling(struct ocores_i2c_bus *i2c)
321 err = ocores_poll_wait(i2c);
323 i2c->state = STATE_ERROR;
327 ret = ocores_isr(-1, i2c);
331 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
332 if (i2c->state == STATE_DONE)
338 static int ocores_xfer_core(struct ocores_i2c_bus *i2c,
343 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
346 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
348 i2c->msg = msgs;
349 i2c->pos = 0;
350 i2c->nmsgs = num;
351 i2c->state = STATE_START;
353 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
354 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
357 ocores_process_polling(i2c);
359 return (i2c->state == STATE_DONE) ? num : -EIO;
437 static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg)
444 rd = in_be32(i2c->base + (rreg << i2c->reg_shift));
451 static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value)
459 curr = in_be32(i2c->base + (rreg << i2c->reg_shift));
467 out_be32(i2c->base + (rreg << i2c->reg_shift), wr);
568 debug("GRLIB variant of i2c-ocores\n");
608 if (device_is_compatible(dev, "sifive,fu540-c000-i2c"))
623 { .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES },
625 { .compatible = "sifive,fu540-c000-i2c" },