Lines Matching refs:status
278 unsigned int status;
283 status = ddr3_init_main();
284 if (status == MV_DDR3_TRAINING_ERR_BAD_SAR)
286 if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP)
288 if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT)
290 if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT)
292 if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP)
294 if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL)
296 if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH)
298 if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE)
300 if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH)
302 if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE)
303 DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8);
305 return status;
362 __maybe_unused int status;
508 status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width);
509 if (MV_OK != status) {
511 return status;
609 status = ddr3_hw_training(target_freq, ddr_width,
613 if (MV_OK != status) {
615 return status;
632 status = ddr3_hw_training(target_freq, ddr_width,
636 if (MV_OK != status) {
638 return status;