Lines Matching refs:result
366 u32 result = 0;
375 result = tm->timing_data[MV_DDR_TRCD_MIN];
377 result = speed_bin_table_t_rcd_t_rp[index];
381 result = tm->timing_data[MV_DDR_TRAS_MIN];
384 result = 35000;
386 result = 34000;
388 result = 33000;
390 result = 32000;
395 result = tm->timing_data[MV_DDR_TRC_MIN];
397 result = speed_bin_table_t_rc[index];
402 result = tm->timing_data[MV_DDR_TRRD_S_MIN];
405 result = 5000;
407 result = 4200;
409 result = 3700;
411 result = 3500;
413 result = 3000;
415 result = 2700;
417 result = 2500;
422 result = tm->timing_data[MV_DDR_TRRD_S_MIN];
425 result = 6000;
427 result = 5300;
434 result = tm->timing_data[MV_DDR_TRRD_L_MIN];
437 result = 6000;
439 result = 5300;
441 result = 4900;
446 result = tm->timing_data[MV_DDR_TRRD_L_MIN];
449 result = 7500;
451 result = 6400;
455 result = 5000;
459 result = tm->timing_data[MV_DDR_TFAW_MIN];
462 result = 20000;
464 result = 17000;
466 result = 15000;
468 result = 13000;
470 result = 12000;
472 result = 10875;
474 result = 10000;
479 result = tm->timing_data[MV_DDR_TFAW_MIN];
482 result = 25000;
484 result = 23000;
486 result = 21000;
491 result = tm->timing_data[MV_DDR_TFAW_MIN];
494 result = 35000;
496 result = 30000;
500 result = 2500;
503 result = tm->timing_data[MV_DDR_TWTR_S_MIN];
507 result = 7500;
510 result = tm->timing_data[MV_DDR_TWTR_L_MIN];
514 result = 15000;
517 result = tm->timing_data[MV_DDR_TWR_MIN];
520 result = 24000;
523 if (mv_ddr_tdllk_get(freq, &result))
524 result = 0;
528 result = tm->timing_data[MV_DDR_TCCD_L_MIN];
531 result = 6250;
533 result = 5355;
535 result = 5000;
543 return result;