marvell/a38x/mv_ddr4_training_db.c

43 /* non-dbi mode - table for cl values per frequency for each speed bin index */
74 u32 mv_ddr_cl_val_get(u32 index, u32 freq)
76 	return cl_table[index].cl_val[freq];
79 /* dbi mode - table for cl values per frequency for each speed bin index */
109 /* table for cwl values per speed bin index */
139 u32 mv_ddr_cwl_val_get(u32 index, u32 freq)
141 	return cwl_table[index].cl_val[freq];
361 /* return speed bin value for selected index and element */
362 unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element)
377 			result = speed_bin_table_t_rcd_t_rp[index];
383 			if (index <= SPEED_BIN_DDR_1600L)
385 			else if (index <= SPEED_BIN_DDR_1866N)
387 			else if (index <= SPEED_BIN_DDR_2133R)
397 			result = speed_bin_table_t_rc[index];
404 			if (index <= SPEED_BIN_DDR_1600L)
406 			else if (index <= SPEED_BIN_DDR_1866N)
408 			else if (index <= SPEED_BIN_DDR_2133R)
410 			else if (index <= SPEED_BIN_DDR_2400U)
412 			else if (index <= SPEED_BIN_DDR_2666W)
414 			else if (index <= SPEED_BIN_DDR_2933AA)
424 			if (index <= SPEED_BIN_DDR_1600L)
436 			if (index <= SPEED_BIN_DDR_1600L)
438 			else if (index <= SPEED_BIN_DDR_2133R)
448 			if (index <= SPEED_BIN_DDR_1600L)
461 			if (index <= SPEED_BIN_DDR_1600L)
463 			else if (index <= SPEED_BIN_DDR_1866N)
465 			else if (index <= SPEED_BIN_DDR_2133R)
467 			else if (index <= SPEED_BIN_DDR_2400U)
469 			else if (index <= SPEED_BIN_DDR_2666W)
471 			else if (index <= SPEED_BIN_DDR_2933AA)
481 			if (index <= SPEED_BIN_DDR_1600L)
483 			else if (index <= SPEED_BIN_DDR_1866N)
493 			if (index <= SPEED_BIN_DDR_1600L)
530 			if (index <= SPEED_BIN_DDR_1600L)
532 			else if (index <= SPEED_BIN_DDR_2133R)