marvell/a38x/ddr3_training_leveling.c

41 	u32 bus_num, if_id, cl_val;
54 		for (bus_num = 0; bus_num < MAX_BUS_NUM; bus_num++)
56 				rl_values[effective_cs][bus_num][if_id] = 0;
203 			for (bus_num = 0;
204 			     bus_num < octets_per_if_num;
205 			     bus_num++) {
206 				VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
210 				     mask_results_pup_reg_map[bus_num],
214 							if_id, effective_cs, bus_num));
223 						      [bus_num], data_read,
225 					rl_values[effective_cs][bus_num]
269 			for (bus_num = 0;
270 			     bus_num < octets_per_if_num;
271 			     bus_num++) {
272 				VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
274 				data = rl_values[effective_cs][bus_num][if_id];
281 						   bus_num, DDR_PHY_DATA,
400 	u32 bus_num, if_id, cl_val, bit_num;
418 		for (bus_num = 0;
419 		     bus_num <= octets_per_if_num; bus_num++) {
420 			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
421 			per_bit_rl_pup_status[if_id][bus_num] = 0;
422 			data2_write[if_id][bus_num] = 0;
426 				      bus_num, DDR_PHY_DATA,
428 				      &phyreg3_arr[if_id][bus_num]));
574 			for (bus_num = 0;
575 			     bus_num < octets_per_if_num;
576 			     bus_num++) {
577 				VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
579 				if (per_bit_rl_pup_status[if_id][bus_num]
590 						     [bus_num * 8 + bit_num],
596 								  bus_num,
606 								  [bus_num * 8 +
624 							if (data > data2_write[if_id][bus_num])
627 									[bus_num] =
632 					if (data2_write[if_id][bus_num] <=
636 							[bus_num] = 1;
648 				for (bus_num = 0;
649 				     bus_num < octets_per_if_num;
650 				     bus_num++) {
652 							bus_num);
654 					    [bus_num] != 1) {
662 							  bus_num, DDR_PHY_DATA,
665 							   [bus_num] +
681 		for (bus_num = 0; bus_num < octets_per_if_num;
682 		     bus_num++) {
683 			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
684 			if (per_bit_rl_pup_status[if_id][bus_num] == 1)
689 						   bus_num, DDR_PHY_DATA,
692 						   [bus_num]);
700 		 * as_bus_params[bus_num].cs_bitmask;