marvell/a38x/ddr3_training_bist.c

20 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
44 	ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset);
48 		pattern_table[pattern].tx_burst_size : 0;
52 		      pattern_table[pattern].num_of_phases_tx, tx_burst_size,
53 		      pattern_table[pattern].num_of_phases_rx,
118 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
130 		ret = ddr3_tip_bist_activate(dev_num, pattern,
141 		ret = ddr3_tip_bist_activate(dev_num, pattern,
224 static int mv_ddr_tip_bist(enum hws_dir dir, u32 val, enum hws_pattern pattern, u32 cs, u32 *result)
234 			     TIP_ITERATION_NUM, pattern, EDGE_FP, CS_SINGLE, cs, &training_result);
441 static int mv_ddr_odpg_bist_prepare(enum hws_pattern pattern, enum hws_access_type access_type,
463 	if (pattern == PATTERN_ZERO || pattern == PATTERN_ONE)
465 	if (pattern == PATTERN_00 || pattern == PATTERN_FF)
467 		ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset);
469 		mv_ddr_load_dm_pattern_to_odpg(access_type, pattern, dm_dir);
473 		tx_burst_size = pattern_table[pattern].tx_burst_size;
481 	ddr3_tip_configure_odpg(0, access_type, 0, dir, pattern_table[pattern].num_of_phases_tx,
482 				tx_burst_size, pattern_table[pattern].num_of_phases_rx, burst_delay,
490 int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector)
510 	/* fill memory with base pattern */
512 	mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE,
513 				 bist_offset, cs, pattern_table[pattern].num_of_phases_tx,
515 				 (pattern == PATTERN_ZERO) ? DM_DIR_DIRECT : DM_DIR_INVERSE);
517 				 (pattern == PATTERN_00) ? DM_DIR_DIRECT : DM_DIR_INVERSE);
527 					pattern_table[pattern].num_of_phases_tx,
528 					pattern_table[pattern].tx_burst_size,
529 					pattern_table[pattern].num_of_phases_rx,
547 	/* fill memory with vref pattern to increment addr using odpg bist */
549 				 bist_offset, cs, pattern_table[pattern].num_of_phases_tx,
551 				 (pattern == PATTERN_ZERO) ? DM_DIR_DIRECT : DM_DIR_INVERSE);
553 				 (pattern == PATTERN_00) ? DM_DIR_DIRECT : DM_DIR_INVERSE);
564 					pattern_table[pattern].num_of_phases_tx,
565 					pattern_table[pattern].tx_burst_size,
566 					pattern_table[pattern].num_of_phases_rx,
592 	/* read and validate bist (comparing with the base pattern) */
597 		mv_ddr_pattern_start_addr_set(pattern_table, pattern, odpg_addr);
598 		mv_ddr_tip_bist(OPER_READ, 0, pattern, 0, &result);