marvell/a38x/ddr3_training.c

832 	int status = 1;
835 	status &= ddr3_tip_validate_algo_var(ck_delay, PARAM_UNDEFINED, "ck_delay");
836 	status &= ddr3_tip_validate_algo_var(phy_reg3_val, PARAM_UNDEFINED, "phy_reg3_val");
837 	status &= ddr3_tip_validate_algo_var(g_rtt_nom, PARAM_UNDEFINED, "g_rtt_nom");
838 	status &= ddr3_tip_validate_algo_var(g_dic, PARAM_UNDEFINED, "g_dic");
839 	status &= ddr3_tip_validate_algo_var(odt_config, PARAM_UNDEFINED, "odt_config");
840 	status &= ddr3_tip_validate_algo_var(g_zpri_data, PARAM_UNDEFINED, "g_zpri_data");
841 	status &= ddr3_tip_validate_algo_var(g_znri_data, PARAM_UNDEFINED, "g_znri_data");
842 	status &= ddr3_tip_validate_algo_var(g_zpri_ctrl, PARAM_UNDEFINED, "g_zpri_ctrl");
843 	status &= ddr3_tip_validate_algo_var(g_znri_ctrl, PARAM_UNDEFINED, "g_znri_ctrl");
844 	status &= ddr3_tip_validate_algo_var(g_zpodt_data, PARAM_UNDEFINED, "g_zpodt_data");
845 	status &= ddr3_tip_validate_algo_var(g_znodt_data, PARAM_UNDEFINED, "g_znodt_data");
846 	status &= ddr3_tip_validate_algo_var(g_zpodt_ctrl, PARAM_UNDEFINED, "g_zpodt_ctrl");
847 	status &= ddr3_tip_validate_algo_var(g_znodt_ctrl, PARAM_UNDEFINED, "g_znodt_ctrl");
850 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func,
852 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write,
854 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read,
856 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write,
858 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read,
860 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func,
862 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_set_freq_divider_func,
864 	status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_clock_ratio,
867 	status &= ddr3_tip_validate_algo_ptr(dq_map_table, NULL, "dq_map_table");
868 	status &= ddr3_tip_validate_algo_var(dfs_low_freq, 0, "dfs_low_freq");
870 	return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
910 	int status;
912 	status = ddr3_post_run_alg();
913 	if (MV_OK != status) {
914 		printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
915 		return status;
937 	int status = MV_OK;
939 	status = ddr3_pre_algo_config();
940 	if (MV_OK != status) {
941 		printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
942 		return status;
951 		status = ddr3_tip_ddr3_auto_tune(dev_num);
954 	if (status != MV_OK) {
957 				   status));
958 		return status;
961 	status = ddr3_post_algo_config();
962 	if (MV_OK != status) {
963 		printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
964 		return status;
967 	return status;
2604 	int status;
2615 	status = ddr3_tip_ddr3_training_main_flow(dev_num);
2630 	if (status != MV_OK) {
2649 	if (((status == MV_FAIL) && (is_auto_tune_fail == 0)) ||
2650 	    ((status == MV_OK) && (is_auto_tune_fail == 1))) {
2658 				   "are not synced (status 0x%x  result DB %d)\n",
2659 				   status, is_auto_tune_fail));
2662 	if ((status != MV_OK) || (is_auto_tune_fail == 1))