Lines Matching defs:freq
378 enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
416 t_ckclk = (MEGA / mv_ddr_freq_get(freq));
593 ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
698 adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64);
1248 u32 freq = mv_ddr_freq_get(frequency);
1251 ("dev %d access %d IF %d freq %d\n", dev_num,
1293 tclk = 1000000 / freq;
1310 ("Freq_set dev 0x%x access 0x%x if 0x%x freq 0x%x speed %d:\n\t",
1413 /* Low freq*/
1419 /* Middle or target freq */
1440 t_ckclk = (MEGA / freq);
1513 mdelay(100 / (freq / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ)));
1540 adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq * 64));
1691 u32 freq = mv_ddr_freq_get(frequency);
1696 t_ckclk = (MEGA / freq);
1698 t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency));
1837 u32 freq = mv_ddr_freq_get(frequency);
1843 t_ckclk = (MEGA / freq);
2137 enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
2160 (u8)dev_num, if_id, freq);
2168 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2196 ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);