ddr/fsl/options.c

27 void __weak fsl_ddr_board_options(memctl_options_t *popts,
745 			memctl_options_t *popts,
839 		popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
840 		popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
841 		popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
842 		popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
844 		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
845 		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
847 		popts->cs_local_opts[i].auto_precharge = 0;
856 	popts->memctl_interleaving = 0;
864 	popts->memctl_interleaving_mode = 0;
885 	popts->ba_intlv_ctl = 0;
888 	popts->registered_dimm_en = common_dimm->all_dimms_registered;
893 	popts->ecc_mode = 0;		  /* 0 = disabled, 1 = enabled */
897 			popts->ecc_mode = 1;
899 		popts->ecc_mode = 1;
902 	popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
910 	popts->dqs_config = 0;
912 	popts->dqs_config = 1;
916 	popts->self_refresh_in_sleep = 1;
919 	popts->dynamic_power = 0;
930 			popts->data_bus_width = 0;
933 			popts->data_bus_width = 1;
942 			popts->data_bus_width = 0;
944 			popts->data_bus_width = 1;
946 			popts->data_bus_width = 2;
954 	popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
959 	popts->otf_burst_chop_en = 0;	/* on-the-fly burst chop disable */
960 	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
962 	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
964 		popts->otf_burst_chop_en = 0;
965 		popts->burst_length = DDR_BL8;
967 		popts->otf_burst_chop_en = 1;	/* on-the-fly burst chop */
968 		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
972 	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
979 			popts->mirrored_dimm = pdimm[i].mirrored_dimm;
989 	popts->cas_latency_override = 0;
990 	popts->cas_latency_override_value = 3;
991 	if (popts->cas_latency_override) {
993 		       popts->cas_latency_override_value);
997 	popts->use_derated_caslat = 0;
1000 	popts->additive_latency_override = 0;
1001 	popts->additive_latency_override_value = 3;
1002 	if (popts->additive_latency_override) {
1004 		       popts->additive_latency_override_value);
1015 	popts->twot_en = 0;
1016 	popts->threet_en = 0;
1019 	if (popts->registered_dimm_en)
1020 		popts->ap_en = 1; /* 0 = disable,  1 = enable */
1022 		popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
1026 			if (popts->registered_dimm_en ||
1028 				popts->ap_en = 1;
1041 	popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1052 	popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1059 	popts->tfaw_window_four_activates_ps = 37500;
1062 	popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1064 	popts->zq_en = 0;
1065 	popts->wrlvl_en = 0;
1072 	popts->wrlvl_en = 1;
1073 	popts->zq_en = 1;
1074 	popts->wrlvl_override = 0;
1101 		popts->memctl_interleaving = 0;
1104 	popts->memctl_interleaving = 1;
1106 	popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1107 	popts->memctl_interleaving = 1;
1116 		popts->memctl_interleaving = 0;
1121 		popts->memctl_interleaving_mode =
1124 		popts->memctl_interleaving =
1130 		popts->memctl_interleaving_mode =
1133 		popts->memctl_interleaving =
1139 		popts->memctl_interleaving_mode =
1142 		popts->memctl_interleaving =
1148 		popts->memctl_interleaving_mode =
1151 		popts->memctl_interleaving =
1158 		popts->memctl_interleaving_mode =
1163 		popts->memctl_interleaving_mode =
1168 		popts->memctl_interleaving_mode =
1174 		popts->memctl_interleaving_mode =
1179 		popts->memctl_interleaving_mode =
1184 		popts->memctl_interleaving_mode =
1188 		popts->memctl_interleaving = 0;
1203 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1206 			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1209 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1212 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1215 			popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1218 		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1222 				popts->ba_intlv_ctl = 0;
1233 				popts->ba_intlv_ctl = 0;
1239 				popts->ba_intlv_ctl = 0;
1248 				popts->ba_intlv_ctl = 0;
1257 				popts->ba_intlv_ctl = 0;
1263 				popts->ba_intlv_ctl = 0;
1272 				popts->ba_intlv_ctl = 0;
1279 				popts->ba_intlv_ctl = 0;
1287 			popts->ba_intlv_ctl = 0;
1294 			popts->addr_hash = 0;
1297 			popts->addr_hash = 1;
1301 		popts->quad_rank_present = 1;
1303 	popts->package_3ds = pdimm->package_3ds;
1307 	if (popts->registered_dimm_en) {
1308 		popts->rcw_override = 1;
1309 		popts->rcw_1 = 0x000a5a00;
1311 			popts->rcw_2 = 0x00000000;
1313 			popts->rcw_2 = 0x00100000;
1315 			popts->rcw_2 = 0x00200000;
1317 			popts->rcw_2 = 0x00300000;
1321 	fsl_ddr_board_options(popts, pdimm, ctrl_num);