ddr/fsl/mpc85xx_ddr_gen3.c

83 	debug("Workaround for ERRATUM_DDR111_DDR134\n");
95 			debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
182 		if (regs->debug[i]) {
183 			debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
184 			out_be32(&ddr->debug[i], regs->debug[i]);
189 	out_be32(&ddr->debug[12], 0x00000015);
190 	out_be32(&ddr->debug[21], 0x24000000);
212 	debug("Workaround for ERRATUM_DDR_A003\n");
215 		out_be32(&ddr->debug[2], 0x00000400);
220 		save1 = in_be32(&ddr->debug[12]);
221 		save2 = in_be32(&ddr->debug[21]);
222 		out_be32(&ddr->debug[12], 0x00000015);
223 		out_be32(&ddr->debug[21], 0x24000000);
228 		while (!(in_be32(&ddr->debug[1]) & 0x2))
340 		out_be32(&ddr->debug[2], 0x0);
344 		out_be32(&ddr->debug[12], save1);
345 		out_be32(&ddr->debug[21], save2);
358 			val32 = ddr_in32(&ddr->debug[28]);
360 			ddr_out32(&ddr->debug[28], val32);
362 		debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
370 	val32 = in_be32(&ddr->debug[18]) | 0x2;
371 	out_be32(&ddr->debug[18], val32);
373 	out_be32(&ddr->debug[28], 0x30000000);
374 	debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
379 	val32 = in_be32(&ddr->debug[28]);
390 	out_be32(&ddr->debug[28], val32);
391 	debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
399 	debug("Workaround for ERRATUM_DDR_115\n");
403 		setbits_be32(&ddr->debug[0], 1);
407 	debug("Workaround for ERRATUM_DDR111_DDR134\n");
415 	debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
419 	debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
423 	setbits_be32(&ddr->debug[2], 0x400);
424 	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
482 	debug("total %d GB\n", total_gb_size_per_controller);
483 	debug("Need to wait up to %d * 10ms\n", timeout);
499 	clrbits_be32(&ddr->debug[2], 0x400);
500 	debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
505 	debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
509 	setbits_be32(&ddr->debug[0], 0x10000);
510 	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
514 	debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
518 	out_be32(&ddr->debug[5], 0x9f9f9f9f);
519 	debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
522 	out_be32(&ddr->debug[6], 0x9f9f9f9f);
523 	debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
526 	setbits_be32(&ddr->debug[1], 0x800);
527 	debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
530 	while (in_be32(&ddr->debug[1]) & 0x800)
534 	clrbits_be32(&ddr->debug[0], 0x10000);
535 	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
540 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
544 	setbits_be32(&ddr->debug[1], 0x400);
545 	debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
548 	while (in_be32(&ddr->debug[1]) & 0x400)
552 	debug("Wait for %d * 10ms\n", timeout_save);
558 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
562 	debug("Need to wait up to %d * 10ms\n", timeout);
574 	debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
579 		debug("Change cs%d_bnds back to 0x%08x\n",