ddr/fsl/ddr4_dimm_params.c

7  * from ddr3 spd, please refer to the spec
28  * where: sdram capacity  = spd byte4[3:0]
29  *        primary bus width = spd byte13[2:0]
30  *        sdram width = spd byte12[2:0]
31  *        Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
32  *                                 spd byte12{5:3] * spd byte6[6:4] for 3DS
35  * where Number of Package Ranks = spd byte12[5:3]
88 compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
98 	if ((spd->density_banks & 0xf) <= 7)
99 		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
100 	if ((spd->bus_width & 0x7) < 4)
101 		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
102 	if ((spd->organization & 0x7) < 4)
103 		nbit_sdram_width = (spd->organization & 0x7) + 2;
104 	package_3ds = (spd->package_type & 0x3) == 0x2;
105 	if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */
110 		die_count = (spd->package_type >> 4) & 0x7;
126  * Compute DIMM parameters based upon the SPD information in spd.
131 					 const generic_spd_eeprom_t *spd,
145 	if (spd->mem_type) {
146 		if (spd->mem_type != SPD_MEMTYPE_DDR4) {
156 	retval = ddr4_spd_check(spd);
168 	if ((spd->info_size_crc & 0xF) > 2)
169 		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
172 	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
173 	pdimm->rank_density = compute_ranksize(spd);
175 	pdimm->die_density = spd->density_banks & 0xf;
176 	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
177 	if ((spd->bus_width >> 3) & 0x3)
183 	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
184 	pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
185 			     (spd->package_type >> 4) & 0x7 : 0;
190 	switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
194 		if (spd->mod_section.registered.reg_map & 0x1)
196 		val = spd->mod_section.registered.ca_stren;
199 		val = spd->mod_section.registered.clk_stren;
221 		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
223 		if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
224 		    (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
227 				if (spd->mapping[i] == udimm_rc_e_dq[i])
231 				      60 + i, spd->mapping[i],
233 				ptr = (u8 *)&spd->mapping[i];
242 		printf("unknown module_type 0x%02X\n", spd->module_type);
247 	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
248 	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
249 	pdimm->bank_addr_bits = ((spd->density_banks >> 4) & 0x3) + 2;
250 	pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
276 	if ((spd->timebases & 0xf) == 0x0) {
285 	pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
288 	pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
298 	pdimm->caslat_x  = (spd->caslat_b1 << 7)	|
299 			   (spd->caslat_b2 << 15)	|
300 			   (spd->caslat_b3 << 23);
302 	BUG_ON(spd->caslat_b4 != 0);
307 	pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
312 	pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
317 	pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
320 	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
321 			  spd->tras_min_lsb) * pdimm->mtb_ps;
324 	pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
325 				   spd->trc_min_lsb), spd->fine_trc_min);
327 	pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
329 	pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
331 	pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
334 	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
338 	pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
340 	pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
342 	pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
362 		pdimm->dq_mapping[i] = spd->mapping[i];
364 	pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;