ddr/fsl/ddr3_dimm_params.c

7  * from ddr3 spd, please refer to the spec
24  * where: sdram capacity  = spd byte4[3:0]
25  *        primary bus width = spd byte8[2:0]
26  *        sdram width = spd byte7[2:0]
54 compute_ranksize(const ddr3_spd_eeprom_t *spd)
62 	if ((spd->density_banks & 0xf) < 7)
63 		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
64 	if ((spd->bus_width & 0x7) < 4)
65 		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
66 	if ((spd->organization & 0x7) < 4)
67 		nbit_sdram_width = (spd->organization & 0x7) + 2;
80  * Compute DIMM parameters based upon the SPD information in spd.
85 					 const ddr3_spd_eeprom_t *spd,
94 	if (spd->mem_type) {
95 		if (spd->mem_type != SPD_MEMTYPE_DDR3) {
104 	retval = ddr3_spd_check(spd);
116 	if ((spd->info_size_crc & 0xF) > 1)
117 		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
120 	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
121 	pdimm->rank_density = compute_ranksize(spd);
123 	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
124 	if ((spd->bus_width >> 3) & 0x3)
130 	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
135 	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
142 			u8 rcw = spd->mod_section.registered.rcw[i/2];
159 		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
164 		printf("unknown module_type 0x%02X\n", spd->module_type);
169 	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
170 	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
171 	pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
195 	mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
204 		((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
214 	pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
215 		(spd->fine_tck_min * ftb_10th_ps) / 10;
223 	pdimm->caslat_x  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
233 	pdimm->taa_ps = spd->taa_min * mtb_ps +
234 		(spd->fine_taa_min * ftb_10th_ps) / 10;
241 	pdimm->twr_ps = spd->twr_min * mtb_ps;
251 	pdimm->trcd_ps = spd->trcd_min * mtb_ps +
252 		(spd->fine_trcd_min * ftb_10th_ps) / 10;
260 	pdimm->trrd_ps = spd->trrd_min * mtb_ps;
270 	pdimm->trp_ps = spd->trp_min * mtb_ps +
271 		(spd->fine_trp_min * ftb_10th_ps) / 10;
280 	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
290 	pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
291 			* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
299 	pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
306 	pdimm->twtr_ps = spd->twtr_min * mtb_ps;
313 	pdimm->trtp_ps = spd->trtp_min * mtb_ps;
321 	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
334 	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)