Lines Matching refs:RB
37 * Helper macro RB() takes care of converting the register
45 #define RB(_reg, _bit) ((struct regbit) { \
274 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),
275 RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),
276 RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),
277 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),
278 RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),
279 RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),
280 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),
281 RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),
282 RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),
283 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),
284 RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),
285 RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),
286 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),
287 RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),
288 RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),
289 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),
290 RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),
291 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
292 D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),
293 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
294 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
295 D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),
296 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
297 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
298 D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
299 RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),
300 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
301 D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
302 RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),
303 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
304 D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),
305 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
306 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
307 D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),
308 RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),
309 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
310 D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),
311 RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),
312 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
313 D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),
314 RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),
315 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
316 D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),
317 RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),
318 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
319 D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),
320 RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),
321 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
322 D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),
323 RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),
324 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
325 D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),
326 RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),
327 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
328 D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),
329 RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),
330 RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),
331 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),
332 RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),
333 RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),
334 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),
335 RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),
336 RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),
337 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),
338 RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),
339 RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),
340 D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),
341 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
342 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
343 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),
344 RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),
345 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
346 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),
347 RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
348 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
349 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),
350 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
351 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
352 D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),
353 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
354 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
355 D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),
356 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
357 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
358 D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),
359 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
360 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
361 D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),
362 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
363 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
364 D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),
365 RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),
366 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
367 D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
368 RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),
369 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
370 D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
371 RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),
372 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
373 D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),
374 RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),
375 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
376 D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),
377 RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),
378 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
379 D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),
380 RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),
381 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
382 D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),
383 RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),
384 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
385 D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),
386 RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),
387 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
389 D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),
390 RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),
391 RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),
392 D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),
393 RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),
394 RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),
395 D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),
396 RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),
397 RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),
398 D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),
399 RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),
400 RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),
401 D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),
402 RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),
403 RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),
404 D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),
405 RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),
406 RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),
407 D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),
408 RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),
409 RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),
410 D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),
411 RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),
412 RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),
413 D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),
414 RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),
415 RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),
416 D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),
417 RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),
418 RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),
419 D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),
420 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
421 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
422 D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
423 RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),
424 RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),
425 D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
426 RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),
427 RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),
435 D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
436 RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),
437 RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),
438 D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
439 RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),
440 RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),
441 D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),
442 RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),
443 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
444 D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),
445 RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),
446 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
447 D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
448 RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),
449 RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),
450 D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),
451 RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),
452 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
453 D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),
454 RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),
455 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
457 D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),
458 RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),
459 RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),
460 D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),
461 RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),
462 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
463 D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),
464 RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),
465 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
466 D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),
467 RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
468 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
469 D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),
470 RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),
471 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
472 D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),
473 RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),
474 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
475 D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),
476 RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),
477 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
478 D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),
479 RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),
480 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
481 D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),
482 RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),
483 RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),
484 D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),
485 RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),
486 RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),
487 D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),
488 RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),
489 RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),
490 D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),
491 RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),
492 RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),
493 D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),
494 RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),
495 RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),
496 D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),
497 RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),
498 RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),
499 D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),
500 RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),
501 RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),
502 D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),
503 RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),
504 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
505 D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),
506 RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),
507 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
508 D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),
509 RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),
510 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
511 D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),
512 RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),
513 RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),
514 D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),
515 RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),
516 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
517 D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),
518 RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),
519 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
520 D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),
521 RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),
522 RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),
523 D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),
524 RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),
525 RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),
526 D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),
527 RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),
528 RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),
529 D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),
530 RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),
531 RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),
532 D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),
533 RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),
534 RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),
535 D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),
536 RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),
537 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
538 D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),
539 RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),
540 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
541 D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),
542 RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),
543 RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),
544 D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),
545 RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),
546 RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),
547 D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),
548 RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),
549 RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),
550 D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),
551 RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),
552 RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),
553 D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),
554 RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),
555 RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),
556 D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),
557 RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),
558 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
559 D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
560 RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),
561 RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),
562 D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
563 RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),
564 RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),
565 D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),
566 RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),
567 RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),
568 D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),
569 RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),
570 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
571 D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),
572 RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),
573 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
574 D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),
575 RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),
576 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
577 D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),
578 RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),
579 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
580 D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),
581 RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),
582 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
583 D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),
584 RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),
585 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
586 D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),
587 RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),
588 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
589 D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),
590 RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),
591 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
592 D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),
593 RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),
594 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
595 D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),
596 RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),
597 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
598 D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),
599 RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),
600 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
601 D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),
602 RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),
603 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
604 D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),
605 RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),
606 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
607 D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),
608 RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),
609 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
610 D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),
611 RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),
612 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
613 D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),
614 RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),
615 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
627 .dual.sel = RB(0x34, 30),
636 .dual.sel = RB(0xec, 24),
640 RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),
642 RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),
644 RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),
646 RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),
648 RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),
650 RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),
652 RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),
654 RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),