clk/meson/g12a.c

96 	struct regmap *map;
174 	regmap_update_bits(priv->map, gate->reg,
271 	regmap_read(priv->map, parm->reg_off, &reg);
365 	regmap_update_bits(priv->map, parm->reg_off,
478 	regmap_read(priv->map, parm->reg_off, &reg);
550 	regmap_update_bits(priv->map, parm->reg_off,
587 	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
598 	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
666 	regmap_read(priv->map, psdm->reg_off, &reg);
669 	regmap_read(priv->map, pn2->reg_off, &reg);
718 	regmap_read(priv->map, pn->reg_off, &reg);
721 	regmap_read(priv->map, pm->reg_off, &reg);
724 	regmap_read(priv->map, pod->reg_off, &reg);
732 		regmap_read(priv->map, pfrac->reg_off, &reg);
765 	regmap_read(priv->map, pn->reg_off, &reg);
768 	regmap_read(priv->map, pm->reg_off, &reg);
771 	regmap_read(priv->map, pod->reg_off, &reg);
871 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
872 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
873 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
874 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
875 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
876 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
877 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
878 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
880 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
882 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
883 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
885 	regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
886 	regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
984 	priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
985 	if (IS_ERR(priv->map))
986 		return PTR_ERR(priv->map);
992 	regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
993 	regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);