Lines Matching refs:port_mmio

113 	void __iomem *port_mmio = uc_priv->port[port].port_mmio;
121 tmp = readl(port_mmio + PORT_SCR_STAT);
133 static void sunxi_dma_init(void __iomem *port_mmio)
135 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
171 void __iomem *port_mmio;
199 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
200 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
203 tmp = readl(port_mmio + PORT_CMD);
209 writel_with_flush(tmp, port_mmio + PORT_CMD);
218 sunxi_dma_init(port_mmio);
224 cmd = readl(port_mmio + PORT_CMD);
226 writel_with_flush(cmd, port_mmio + PORT_CMD);
238 tmp = readl(port_mmio + PORT_SCR_ERR);
240 writel(tmp, port_mmio + PORT_SCR_ERR);
246 tmp = readl(port_mmio + PORT_TFDATA);
250 tmp = readl(port_mmio + PORT_SCR_STAT);
257 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
270 tmp = readl(port_mmio + PORT_SCR_ERR);
272 writel(tmp, port_mmio + PORT_SCR_ERR);
275 tmp = readl(port_mmio + PORT_IRQ_STAT);
278 writel(tmp, port_mmio + PORT_IRQ_STAT);
283 tmp = readl(port_mmio + PORT_SCR_STAT);
434 static int wait_spinup(void __iomem *port_mmio)
441 tf_data = readl(port_mmio + PORT_TFDATA);
452 void __iomem *port_mmio = pp->port_mmio;
458 port_status = readl(port_mmio + PORT_SCR_STAT);
500 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
501 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
503 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
504 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
507 sunxi_dma_init(port_mmio);
512 PORT_CMD_START, port_mmio + PORT_CMD);
520 return wait_spinup(port_mmio);
529 void __iomem *port_mmio = pp->port_mmio;
541 port_status = readl(port_mmio + PORT_SCR_STAT);
556 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
558 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
915 void __iomem *port_mmio = pp->port_mmio;
927 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
929 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,