Lines Matching refs:u8
15 u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
16 u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
17 u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
18 u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
19 u8 hw_ver; /* 0x04 - PCBA Version Register */
20 u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
21 u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
22 u8 res0; /* 0x07 - not used */
23 u8 vbank; /* 0x08 - Flash Bank Selection Control Register */
24 u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */
25 u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */
26 u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */
27 u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */
28 u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/
29 u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
30 u8 res1; /* 0x0f - not used */
42 u8 cpld_read(unsigned int reg);
43 void cpld_write(unsigned int reg, u8 value);