Lines Matching defs:NA

152 #define NA		0xff
157 .confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
158 (((hysctl) != NA) ? hysctl << 24 : 0) | \
159 (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
160 (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
161 (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
162 (((odt_en) != NA) ? odt_en << 17 : 0) | \
164 .confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
165 (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
166 (((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
167 (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
168 (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
169 (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
173 ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
182 .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
183 (((glitch) != NA) ? (glitch << 26) : 0) | \
184 (((term) != NA) ? (term << 20) : 0) | \
187 (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
188 (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
190 .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
191 (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
192 (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
194 (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
195 (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
196 (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
197 .confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
198 (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
199 (((open_drain) != NA) ? open_drain << 3 : 0) | \
200 (((int_type) != NA) ? int_type : 0)), \
201 .confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
202 (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
203 (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
204 (((int_type) != NA) ? THREE_BIT : 0)), \
207 ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
210 .misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
211 (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
212 (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
213 (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \