mips/mach-octeon/octeon_qlm.c

123 	cvmx_mio_rst_ctlx_t rst_ctl;
135 	rst_ctl.u64 = csr_rd(CVMX_MIO_RST_CTLX(pcie_port));
137 	rst_ctl.s.prst_link = rc;
138 	rst_ctl.s.rst_link = ep;
139 	rst_ctl.s.prtmode = rc;
140 	rst_ctl.s.rst_drv = rc;
141 	rst_ctl.s.rst_rcv = 0;
142 	rst_ctl.s.rst_chip = ep;
143 	csr_wr(CVMX_MIO_RST_CTLX(pcie_port), rst_ctl.u64);
1717 		cvmx_rst_ctlx_t rst_ctl;
1737 			rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(0));
1738 			rst_ctl.s.rst_drv = 1;
1739 			csr_wr(CVMX_RST_CTLX(0), rst_ctl.u64);
1756 			rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(0));
1757 			rst_ctl.s.rst_drv = 1;
1758 			csr_wr(CVMX_RST_CTLX(0), rst_ctl.u64);
1773 			rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(1));
1774 			rst_ctl.s.rst_drv = 1;
1775 			csr_wr(CVMX_RST_CTLX(1), rst_ctl.u64);
1791 		cvmx_rst_ctlx_t rst_ctl;
1800 			rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(1));
1801 			rst_ctl.s.rst_drv = 1;
1802 			csr_wr(CVMX_RST_CTLX(1), rst_ctl.u64);
1819 			rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(1));
1820 			rst_ctl.s.rst_drv = 1;
1821 			csr_wr(CVMX_RST_CTLX(1), rst_ctl.u64);
1837 			rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(2));
1838 			rst_ctl.s.rst_drv = 1;
1839 			csr_wr(CVMX_RST_CTLX(2), rst_ctl.u64);
4073 	cvmx_rst_ctlx_t rst_ctl;
4077 	rst_ctl.u64 = csr_rd_node(node, CVMX_RST_CTLX(pem));
4078 	rst_ctl.s.prst_link = 0;	  /* Link down causes soft reset */
4079 	rst_ctl.s.rst_link = is_endpoint; /* EP PERST causes a soft reset */
4080 	rst_ctl.s.rst_drv = !is_endpoint; /* Drive if RC */
4081 	rst_ctl.s.rst_rcv = is_endpoint;  /* Only read PERST in EP mode */
4082 	rst_ctl.s.rst_chip = 0;		  /* PERST doesn't pull CHIP_RESET */
4083 	csr_wr_node(node, CVMX_RST_CTLX(pem), rst_ctl.u64);
5848 		cvmx_rst_ctlx_t rst_ctl;
5850 		rst_ctl.u64 = csr_rd_node(node, CVMX_RST_CTLX(pem));
5851 		__setup_pem_reset(node, pem, !rst_ctl.s.host_mode);