Lines Matching refs:offset
12 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (0x00011F0000008000ull + ((offset) & 31) * 16)
24 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (0x00011F0000008450ull + ((offset) & 7) * 16)
25 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (0x00011F00000083B0ull + ((offset) & 7) * 16)
26 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (0x00011F0000008400ull + ((offset) & 7) * 16)
27 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (0x00011F00000084A0ull + ((offset) & 7) * 16)
49 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
50 (0x00011F0000008280ull + ((offset) & 31) * 16 - 16 * 12)
74 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (0x00011F000000A400ull + ((offset) & 31) * 16)
75 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (0x00011F000000A800ull + ((offset) & 31) * 16)
76 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x00011F000000AC00ull + ((offset) & 31) * 16)
77 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x00011F000000B000ull + ((offset) & 31) * 16)
78 #define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (0x00011F000000B400ull + ((offset) & 31) * 16)
79 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (0x00011F000000B800ull + ((offset) & 31) * 16)
80 #define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (0x00011F0000009400ull + ((offset) & 31) * 16)
81 #define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x00011F0000009800ull + ((offset) & 31) * 16)
82 #define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x00011F0000009C00ull + ((offset) & 31) * 16)
95 #define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (0x00011F000000A000ull + ((offset) & 31) * 16)
116 #define CVMX_PEXP_NQM_VFX_ACQ(offset) (0x0001450000000030ull + ((offset) & 2047) * 0x20000ull)
117 #define CVMX_PEXP_NQM_VFX_AQA(offset) (0x0001450000000024ull + ((offset) & 2047) * 0x20000ull)
118 #define CVMX_PEXP_NQM_VFX_ASQ(offset) (0x0001450000000028ull + ((offset) & 2047) * 0x20000ull)
119 #define CVMX_PEXP_NQM_VFX_CAP(offset) (0x0001450000000000ull + ((offset) & 2047) * 0x20000ull)
120 #define CVMX_PEXP_NQM_VFX_CC(offset) (0x0001450000000014ull + ((offset) & 2047) * 0x20000ull)
121 #define CVMX_PEXP_NQM_VFX_CQX_HDBL(offset, block_id) \
122 (0x0001450000001004ull + (((offset) & 31) + ((block_id) & 2047) * 0x4000ull) * 8)
123 #define CVMX_PEXP_NQM_VFX_CSTS(offset) (0x000145000000001Cull + ((offset) & 2047) * 0x20000ull)
124 #define CVMX_PEXP_NQM_VFX_INTMC(offset) (0x0001450000000010ull + ((offset) & 2047) * 0x20000ull)
125 #define CVMX_PEXP_NQM_VFX_INTMS(offset) (0x000145000000000Cull + ((offset) & 2047) * 0x20000ull)
126 #define CVMX_PEXP_NQM_VFX_MSIX_PBA(offset) (0x0001450000010200ull + ((offset) & 2047) * 0x20000ull)
127 #define CVMX_PEXP_NQM_VFX_NSSR(offset) (0x0001450000000020ull + ((offset) & 2047) * 0x20000ull)
128 #define CVMX_PEXP_NQM_VFX_SQX_TDBL(offset, block_id) \
129 (0x0001450000001000ull + (((offset) & 31) + ((block_id) & 2047) * 0x4000ull) * 8)
130 #define CVMX_PEXP_NQM_VFX_VECX_MSIX_ADDR(offset, block_id) \
131 (0x0001450000010000ull + (((offset) & 31) + ((block_id) & 2047) * 0x2000ull) * 16)
132 #define CVMX_PEXP_NQM_VFX_VECX_MSIX_CTL(offset, block_id) \
133 (0x0001450000010008ull + (((offset) & 31) + ((block_id) & 2047) * 0x2000ull) * 16)
134 #define CVMX_PEXP_NQM_VFX_VS(offset) (0x0001450000000008ull + ((offset) & 2047) * 0x20000ull)
135 #define CVMX_PEXP_SLITB_MSIXX_TABLE_ADDR(offset) (0x00011F0000004000ull + ((offset) & 127) * 16)
136 #define CVMX_PEXP_SLITB_MSIXX_TABLE_DATA(offset) (0x00011F0000004008ull + ((offset) & 127) * 16)
137 #define CVMX_PEXP_SLITB_MSIX_MACX_PFX_TABLE_ADDR(offset, block_id) \
138 (0x00011F0000002000ull + ((offset) & 1) * 4096 + ((block_id) & 3) * 0x10ull)
139 #define CVMX_PEXP_SLITB_MSIX_MACX_PFX_TABLE_DATA(offset, block_id) \
140 (0x00011F0000002008ull + ((offset) & 1) * 4096 + ((block_id) & 3) * 0x10ull)
141 #define CVMX_PEXP_SLITB_PFX_PKT_CNT_INT(offset) (0x00011F0000008000ull + ((offset) & 7) * 16)
142 #define CVMX_PEXP_SLITB_PFX_PKT_INT(offset) (0x00011F0000008300ull + ((offset) & 7) * 16)
143 #define CVMX_PEXP_SLITB_PFX_PKT_IN_INT(offset) (0x00011F0000008200ull + ((offset) & 7) * 16)
144 #define CVMX_PEXP_SLITB_PFX_PKT_RING_RST(offset) (0x00011F0000008400ull + ((offset) & 7) * 16)
145 #define CVMX_PEXP_SLITB_PFX_PKT_TIME_INT(offset) (0x00011F0000008100ull + ((offset) & 7) * 16)
146 #define CVMX_PEXP_SLITB_PKTX_PF_VF_MBOX_SIGX(offset, block_id) \
147 (0x00011F0000011000ull + (((offset) & 1) + ((block_id) & 127) * 0x4000ull) * 8)
171 static inline u64 CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
178 return 0x00011F0000010050ull + (offset) * 16;
180 return 0x00011F0000010050ull + (offset) * 16;
182 return 0x00011F0000010050ull + (offset) * 16;
187 return 0x00011F00000106E0ull + (offset) * 16;
189 return 0x00011F00000286E0ull + (offset) * 16;
191 return 0x00011F00000286E0ull + (offset) * 16;
193 return 0x00011F00000286E0ull + (offset) * 16;
244 static inline u64 CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
253 return 0x00011F0000010400ull + (offset) * 16;
257 return 0x00011F0000010400ull + (offset) * 16;
259 return 0x00011F0000028400ull + (offset) * 16;
261 return 0x00011F0000028400ull + (offset) * 16;
263 return 0x00011F0000028400ull + (offset) * 16;
266 static inline u64 CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
275 return 0x00011F00000103E0ull + (offset) * 16;
279 return 0x00011F00000103E0ull + (offset) * 16;
281 return 0x00011F00000283E0ull + (offset) * 16;
283 return 0x00011F00000283E0ull + (offset) * 16;
285 return 0x00011F00000283E0ull + (offset) * 16;
288 static inline u64 CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
297 return 0x00011F0000010420ull + (offset) * 16;
301 return 0x00011F0000010420ull + (offset) * 16;
303 return 0x00011F0000028420ull + (offset) * 16;
305 return 0x00011F0000028420ull + (offset) * 16;
307 return 0x00011F0000028420ull + (offset) * 16;
311 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (0x00011F0000010340ull + ((offset) & 3) * 16)
317 #define CVMX_PEXP_SLI_MACX_PFX_DMA_VF_INT(offset, block_id) \
318 (0x00011F0000027280ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
319 #define CVMX_PEXP_SLI_MACX_PFX_DMA_VF_INT_ENB(offset, block_id) \
320 (0x00011F0000027500ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
321 #define CVMX_PEXP_SLI_MACX_PFX_FLR_VF_INT(offset, block_id) \
322 (0x00011F0000027400ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
323 #define CVMX_PEXP_SLI_MACX_PFX_INT_ENB(offset, block_id) \
324 (0x00011F0000027080ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
325 #define CVMX_PEXP_SLI_MACX_PFX_INT_SUM(offset, block_id) \
326 (0x00011F0000027000ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
327 #define CVMX_PEXP_SLI_MACX_PFX_MBOX_INT(offset, block_id) \
328 (0x00011F0000027380ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
329 #define CVMX_PEXP_SLI_MACX_PFX_PKT_VF_INT(offset, block_id) \
330 (0x00011F0000027300ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
331 #define CVMX_PEXP_SLI_MACX_PFX_PKT_VF_INT_ENB(offset, block_id) \
332 (0x00011F0000027580ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
333 #define CVMX_PEXP_SLI_MACX_PFX_PP_VF_INT(offset, block_id) \
334 (0x00011F0000027200ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
335 #define CVMX_PEXP_SLI_MACX_PFX_PP_VF_INT_ENB(offset, block_id) \
336 (0x00011F0000027480ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
404 static inline u64 CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
413 return 0x00011F00000100E0ull + (offset) * 16 - 16 * 12;
417 return 0x00011F00000100E0ull + (offset) * 16 - 16 * 12;
419 return 0x00011F00000280E0ull + (offset) * 16 - 16 * 12;
421 return 0x00011F00000280E0ull + (offset) * 16 - 16 * 12;
423 return 0x00011F00000280E0ull + (offset) * 16 - 16 * 12;
458 static inline u64 CVMX_PEXP_SLI_MSIXX_TABLE_ADDR(unsigned long offset)
463 return 0x00011F0000016000ull + (offset) * 16;
465 return 0x00011F0000000000ull + (offset) * 16;
468 return 0x00011F0000000000ull + (offset) * 16;
470 return 0x00011F0000000000ull + (offset) * 16;
473 static inline u64 CVMX_PEXP_SLI_MSIXX_TABLE_DATA(unsigned long offset)
478 return 0x00011F0000016008ull + (offset) * 16;
480 return 0x00011F0000000008ull + (offset) * 16;
483 return 0x00011F0000000008ull + (offset) * 16;
485 return 0x00011F0000000008ull + (offset) * 16;
488 #define CVMX_PEXP_SLI_MSIX_MACX_PF_TABLE_ADDR(offset) (0x00011F0000017C00ull + ((offset) & 3) * 16)
489 #define CVMX_PEXP_SLI_MSIX_MACX_PF_TABLE_DATA(offset) (0x00011F0000017C08ull + ((offset) & 3) * 16)
764 static inline u64 CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
773 return 0x00011F0000012400ull + (offset) * 16;
778 return 0x00011F0000012400ull + (offset) * 16;
780 return 0x00011F00000100B0ull + (offset) * 0x20000ull;
782 return 0x00011F00000100B0ull + (offset) * 0x20000ull;
784 return 0x00011F00000100B0ull + (offset) * 0x20000ull;
787 #define CVMX_PEXP_SLI_PKTX_ERROR_INFO(offset) (0x00011F00000100C0ull + ((offset) & 63) * 0x20000ull)
788 static inline u64 CVMX_PEXP_SLI_PKTX_INPUT_CONTROL(unsigned long offset)
793 return 0x00011F0000014000ull + (offset) * 16;
795 return 0x00011F0000010000ull + (offset) * 0x20000ull;
798 return 0x00011F0000010000ull + (offset) * 0x20000ull;
800 return 0x00011F0000010000ull + (offset) * 0x20000ull;
803 static inline u64 CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
812 return 0x00011F0000012800ull + (offset) * 16;
817 return 0x00011F0000012800ull + (offset) * 16;
819 return 0x00011F0000010010ull + (offset) * 0x20000ull;
821 return 0x00011F0000010010ull + (offset) * 0x20000ull;
823 return 0x00011F0000010010ull + (offset) * 0x20000ull;
826 static inline u64 CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
835 return 0x00011F0000012C00ull + (offset) * 16;
840 return 0x00011F0000012C00ull + (offset) * 16;
842 return 0x00011F0000010020ull + (offset) * 0x20000ull;
844 return 0x00011F0000010020ull + (offset) * 0x20000ull;
846 return 0x00011F0000010020ull + (offset) * 0x20000ull;
849 static inline u64 CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
858 return 0x00011F0000013000ull + (offset) * 16;
863 return 0x00011F0000013000ull + (offset) * 16;
865 return 0x00011F0000010030ull + (offset) * 0x20000ull;
867 return 0x00011F0000010030ull + (offset) * 0x20000ull;
869 return 0x00011F0000010030ull + (offset) * 0x20000ull;
872 #define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (0x00011F0000013400ull + ((offset) & 31) * 16)
873 static inline u64 CVMX_PEXP_SLI_PKTX_INT_LEVELS(unsigned long offset)
878 return 0x00011F0000014400ull + (offset) * 16;
880 return 0x00011F00000100A0ull + (offset) * 0x20000ull;
883 return 0x00011F00000100A0ull + (offset) * 0x20000ull;
885 return 0x00011F00000100A0ull + (offset) * 0x20000ull;
888 #define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (0x00011F0000013800ull + ((offset) & 31) * 16)
889 #define CVMX_PEXP_SLI_PKTX_MBOX_INT(offset) (0x00011F0000010210ull + ((offset) & 63) * 0x20000ull)
890 static inline u64 CVMX_PEXP_SLI_PKTX_OUTPUT_CONTROL(unsigned long offset)
895 return 0x00011F0000014800ull + (offset) * 16;
897 return 0x00011F0000010050ull + (offset) * 0x20000ull;
900 return 0x00011F0000010050ull + (offset) * 0x20000ull;
902 return 0x00011F0000010050ull + (offset) * 0x20000ull;
905 static inline u64 CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
914 return 0x00011F0000010C00ull + (offset) * 16;
919 return 0x00011F0000010C00ull + (offset) * 16;
921 return 0x00011F0000010060ull + (offset) * 0x20000ull;
923 return 0x00011F0000010060ull + (offset) * 0x20000ull;
925 return 0x00011F0000010060ull + (offset) * 0x20000ull;
928 #define CVMX_PEXP_SLI_PKTX_PF_VF_MBOX_SIGX(offset, block_id) \
929 (0x00011F0000010200ull + (((offset) & 1) + ((block_id) & 63) * 0x4000ull) * 8)
930 static inline u64 CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
939 return 0x00011F0000011400ull + (offset) * 16;
944 return 0x00011F0000011400ull + (offset) * 16;
946 return 0x00011F0000010070ull + (offset) * 0x20000ull;
948 return 0x00011F0000010070ull + (offset) * 0x20000ull;
950 return 0x00011F0000010070ull + (offset) * 0x20000ull;
953 static inline u64 CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
962 return 0x00011F0000011800ull + (offset) * 16;
967 return 0x00011F0000011800ull + (offset) * 16;
969 return 0x00011F0000010080ull + (offset) * 0x20000ull;
971 return 0x00011F0000010080ull + (offset) * 0x20000ull;
973 return 0x00011F0000010080ull + (offset) * 0x20000ull;
976 static inline u64 CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
985 return 0x00011F0000011C00ull + (offset) * 16;
990 return 0x00011F0000011C00ull + (offset) * 16;
992 return 0x00011F0000010090ull + (offset) * 0x20000ull;
994 return 0x00011F0000010090ull + (offset) * 0x20000ull;
996 return 0x00011F0000010090ull + (offset) * 0x20000ull;
999 #define CVMX_PEXP_SLI_PKTX_VF_INT_SUM(offset) (0x00011F00000100D0ull + ((offset) & 63) * 0x20000ull)
1000 #define CVMX_PEXP_SLI_PKTX_VF_SIG(offset) (0x00011F0000014C00ull + ((offset) & 63) * 16)
1054 static inline u64 CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
1063 return 0x00011F0000012000ull + (offset) * 16;
1068 return 0x00011F0000012000ull + (offset) * 16;
1070 return 0x00011F0000010040ull + (offset) * 0x20000ull;
1072 return 0x00011F0000010040ull + (offset) * 0x20000ull;
1074 return 0x00011F0000010040ull + (offset) * 0x20000ull;
1123 #define CVMX_PEXP_SLI_PKT_MACX_PFX_RINFO(offset, block_id) \
1124 (0x00011F0000029030ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
1125 #define CVMX_PEXP_SLI_PKT_MACX_RINFO(offset) (0x00011F0000011030ull + ((offset) & 3) * 16)
1218 #define CVMX_PEXP_SLI_PORTX_PKIND(offset) (0x00011F0000010800ull + ((offset) & 31) * 16)
1219 static inline u64 CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
1226 return 0x00011F0000013D80ull + (offset) * 16;
1228 return 0x00011F0000013D80ull + (offset) * 16;
1230 return 0x00011F0000013D80ull + (offset) * 16;
1234 return 0x00011F0000013D80ull + (offset) * 16;
1236 return 0x00011F0000023D80ull + (offset) * 16;
1238 return 0x00011F0000023D80ull + (offset) * 16;
1240 return 0x00011F0000023D80ull + (offset) * 16;