mips/mach-octeon/cvmx-helper-sgmii.c

42  * @param index     Index of prot on the interface
46 static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
53 	if (!cvmx_helper_is_port_valid(interface, index))
57 	gmxx_prtx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
59 	csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
67 		csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
70 		cvmx_helper_get_mac_phy_mode(interface, index);
72 		cvmx_helper_get_1000x_mode(interface, index);
73 	csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
77 		csr_rd(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
87 	csr_wr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),
104 			csr_rd(CVMX_PCSX_ANX_ADV_REG(index, interface));
109 		csr_wr(CVMX_PCSX_ANX_ADV_REG(index, interface),
117 				CVMX_PCSX_SGMX_AN_ADV_REG(index, interface));
120 			csr_wr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface),
145  * @param index     Index of prot on the interface
149 static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
157 	if (!cvmx_helper_is_port_valid(interface, index))
168 	control_reg.u64 = csr_rd(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
176 		csr_wr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
179 			    CVMX_PCSX_MRX_CONTROL_REG(index, interface),
182 			      interface, index);
191 	phy_mode = cvmx_helper_get_mac_phy_mode(interface, index);
193 		      !cvmx_helper_get_port_autonegotiation(interface, index));
218 	csr_wr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
219 	csr_rd(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
225 	csr_wr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
228 	mode_1000x = cvmx_helper_get_1000x_mode(interface, index);
230 		csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
233 	csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
247 	if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface),
250 		debug("SGMII%x: Port %d link timeout\n", interface, index);
262  * @param index     Index of prot on the interface
268 __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index,
275 	if (!cvmx_helper_is_port_valid(interface, index))
279 	gmxx_prtx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
282 	csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
285 	if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface),
288 	    CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface),
292 		      interface, index);
297 	gmxx_prtx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
304 		csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
324 		csr_wr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
325 		csr_wr(CVMX_GMXX_TXX_BURST(index, interface), 0);
332 		csr_wr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
333 		csr_wr(CVMX_GMXX_TXX_BURST(index, interface), 0);
340 		csr_wr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
343 			csr_wr(CVMX_GMXX_TXX_BURST(index, interface), 0);
346 			csr_wr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
353 	csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
357 	csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
360 	gmxx_prtx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
364 	csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
382 	int index;
422 	for (index = 0; index < num_ports; index++) {
423 		int ipd_port = cvmx_helper_get_ipd_port(interface, index);
425 		if (!cvmx_helper_is_port_valid(interface, index))
427 		__cvmx_helper_sgmii_hardware_init_one_time(interface, index);
516 	int index;
520 		for (index = 0; index < num_ports; index++) {
525 			if (!cvmx_helper_is_port_valid(interface, index))
529 				csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
531 				cvmx_helper_get_pknd(interface, index);
532 			csr_wr(CVMX_GMXX_PRTX_CFG(index, interface),
537 				csr_rd(CVMX_GMXX_BPID_MAPX(index, interface));
540 				cvmx_helper_get_bpid(interface, index);
541 			csr_wr(CVMX_GMXX_BPID_MAPX(index, interface),
545 			bpid_msk.s.msk_or |= (1 << index);
546 			bpid_msk.s.msk_and &= ~(1 << index);
557 		for (index = 0; index < num_ports; index++) {
558 			if (!cvmx_helper_is_port_valid(interface, index))
561 				csr_rd(CVMX_GMXX_TXX_APPEND(index, interface));
564 			csr_wr(CVMX_GMXX_TXX_APPEND(index, interface),
578 	for (index = 0; index < num_ports; index++) {
583 		if (!cvmx_helper_is_port_valid(interface, index))
589 		append_cfg.u64 = csr_rd(CVMX_GMXX_TXX_APPEND(index, interface));
591 			csr_rd(CVMX_GMXX_TXX_SGMII_CTL(index, interface));
593 		csr_wr(CVMX_GMXX_TXX_SGMII_CTL(index, interface),
597 			csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
599 		csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
620 	int index = cvmx_helper_get_interface_index_num(ipd_port);
627 	if (!cvmx_helper_is_port_valid(interface, index))
634 		if (inf_mode.s.rate & (1 << index))
652 		csr_rd(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
662 		csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
664 	    cvmx_helper_get_port_force_link_up(interface, index)) {
696 	int index = cvmx_helper_get_interface_index_num(ipd_port);
698 	if (!cvmx_helper_is_port_valid(interface, index))
706 		__cvmx_helper_sgmii_hardware_init_link(interface, index);
711 			csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
717 			csr_rd(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
719 		    !cvmx_helper_get_port_autonegotiation(interface, index)) {
725 		csr_wr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
727 		csr_rd(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
733 		csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
735 		csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
738 	return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
760 	int index = cvmx_helper_get_interface_index_num(ipd_port);
764 	if (!cvmx_helper_is_port_valid(interface, index))
768 		csr_rd(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
770 	csr_wr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
774 		csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
776 	csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
779 	__cvmx_helper_sgmii_hardware_init_link(interface, index);