arm/mach-sunxi/dram_sun50i_h616.c

142 static void mctl_set_addrmap(const struct dram_config *config)
146 	u8 cols = config->cols;
147 	u8 rows = config->rows;
148 	u8 ranks = config->ranks;
150 	if (!config->bus_full_width)
296 static bool mctl_phy_write_leveling(const struct dram_config *config)
307 	if (config->bus_full_width)
331 	if (config->ranks == 2) {
336 		if (config->bus_full_width)
351 static bool mctl_phy_read_calibration(const struct dram_config *config)
360 	if (config->bus_full_width)
376 	if (config->ranks == 2) {
411 			   const struct dram_config *config)
435 	if (config->bus_full_width) {
458 	if (config->bus_full_width) {
480 	if (config->ranks == 2) {
491 		if (config->bus_full_width) {
505 static bool mctl_phy_write_training(const struct dram_config *config)
525 	if (config->bus_full_width) {
548 	if (config->bus_full_width) {
569 	if (config->ranks == 2) {
579 		if (config->bus_full_width) {
797 					       const struct dram_config *config)
822 			if (config->ranks == 2) {
834 			if (config->ranks == 2) {
849 			if (config->ranks == 2) {
855 			if (config->ranks == 2) {
875 			  const struct dram_config *config)
887 	if (config->bus_full_width)
941 		mctl_phy_ca_bit_delay_compensation(para, config);
1111 			if (mctl_phy_write_leveling(config))
1121 			if (mctl_phy_read_calibration(config))
1131 			if (mctl_phy_read_training(para, config))
1141 			if (mctl_phy_write_training(config))
1157 			   const struct dram_config *config)
1178 	reg_val = MSTR_ACTIVE_RANKS(config->ranks);
1193 	if (config->bus_full_width)
1199 	if (config->ranks == 2)
1225 	mctl_set_addrmap(config);
1254 	if (!mctl_phy_init(para, config))
1272 			   const struct dram_config *config)
1276 	return mctl_ctrl_init(para, config);
1280 					struct dram_config *config)
1283 	config->cols = 8;
1284 	config->rows = 13;
1295 	config->bus_full_width = 1;
1296 	config->ranks = 2;
1297 	if (mctl_core_init(para, config))
1301 	config->bus_full_width = 1;
1302 	config->ranks = 1;
1303 	if (mctl_core_init(para, config))
1307 	config->bus_full_width = 0;
1308 	config->ranks = 2;
1309 	if (mctl_core_init(para, config))
1313 	config->bus_full_width = 0;
1314 	config->ranks = 1;
1315 	if (mctl_core_init(para, config))
1322 				       struct dram_config *config)
1325 	config->cols = 8;
1326 	config->rows = 18;
1327 	mctl_core_init(para, config);
1329 	for (config->rows = 13; config->rows < 18; config->rows++) {
1331 		if (mctl_mem_matches((1 << (config->rows + config->cols +
1332 					    4 + config->bus_full_width))))
1337 	config->cols = 11;
1338 	mctl_core_init(para, config);
1340 	for (config->cols = 8; config->cols < 11; config->cols++) {
1342 		if (mctl_mem_matches(1 << (config->cols + 1 +
1343 					   config->bus_full_width)))
1348 static unsigned long mctl_calc_size(const struct dram_config *config)
1350 	u8 width = config->bus_full_width ? 4 : 2;
1353 	return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
1381 	struct dram_config config;
1387 	mctl_auto_detect_rank_width(&para, &config);
1388 	mctl_auto_detect_dram_size(&para, &config);
1390 	mctl_core_init(&para, &config);
1392 	size = mctl_calc_size(&config);