Lines Matching refs:spd
160 static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd,
169 spd->sdram_type = 0x03;
170 spd->ibank = 0x03;
174 spd->t_ck = buf->tck_min * mtb;
176 spd_cb->ddrspdclock = 2000000 / spd->t_ck;
179 spd->rank = ((buf->organization & 0x38) >> 3) + 1;
180 if (spd->rank > 2)
183 spd->pagesize = (buf->addressing & 0x07) + 1;
184 if (spd->pagesize > 3)
187 spd->buswidth = 8 << (buf->bus_width & 0x7);
188 if ((spd->buswidth < 16) || (spd->buswidth > 64))
191 spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1;
196 spd->t_xp = ((3 * spd->t_ck) > 6000) ?
197 3 : ((5999 / spd->t_ck) + 1);
198 spd->t_cke = ((3 * spd->t_ck) > 5625) ?
199 3 : ((5624 / spd->t_ck) + 1);
201 spd->t_xp = ((3 * spd->t_ck) > 6000) ?
202 3 : ((5999 / spd->t_ck) + 1);
203 spd->t_cke = ((3 * spd->t_ck) > 5000) ?
204 3 : ((4999 / spd->t_ck) + 1);
210 spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck;
211 spd->t_ckesr = spd->t_cke + 1;
214 spd->cas = cas_latancy((buf->caslat_msb << 8) |
217 spd->t_wr = (buf->twr_min * mtb) / spd->t_ck;
218 spd->t_wr_bin = (spd->t_wr / 2) & 0x07;
220 spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1;
221 spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1;
222 spd->t_rp = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1;
224 spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) *
225 mtb) / spd->t_ck;
227 spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) *
228 mtb) - 1) / spd->t_ck + 1;
230 spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb /
232 spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck;
233 spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck;
235 spd->t_xs = (((spd->t_rfc + 10) * 1000) / spd->t_ck);
236 spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1;
238 spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck;
239 spd->t_rrd2 = ((((buf->tfaw_msb << 8) |
240 buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1;
243 spd->t_mrd = 0x00;
244 spd->t_mod = 0x00;
245 spd->t_wlo = 0x0C;
246 spd->t_wlmrd = 0x28;
247 spd->t_xsdll = 0x200;
248 spd->t_ras_max = 0x0F;
249 spd->t_csta = 0x05;
250 spd->t_dllk = 0x200;
253 if (spd->t_ck >= 2500)
254 spd->cwl = 0;
255 else if (spd->t_ck >= 1875)
256 spd->cwl = 1;
257 else if (spd->t_ck >= 1500)
258 spd->cwl = 2;
259 else if (spd->t_ck >= 1250)
260 spd->cwl = 3;
261 else if (spd->t_ck >= 1071)
262 spd->cwl = 4;
264 spd->cwl = 5;
267 spd->asr = (buf->therm_ref_opt & 0x04) >> 2;
268 spd->pasr = (buf->therm_ref_opt & 0x80) >> 7;
269 spd->t_zqcs = 64;
271 spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250;
272 spd->t_refprd = spd->t_refprd / spd->t_ck;
274 spd->refresh_rate = spd->t_refprd;
275 spd->t_refprd = spd->t_refprd * 5;
279 spd->freqsel = 0x03;
281 spd->freqsel = 0x01;
283 spd->freqsel = 0x00;
285 spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */
286 spd->t_dinit1 = spd->t_xs;
287 spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */
289 spd->t_dinit3 = 1000000 / spd->t_ck;
291 spd->t_pllgs = PLLGS_VAL + 1;
292 spd->t_pllpd = PLLPD_VAL + 1;
293 spd->t_plllock = PLLLOCK_VAL + 1;
294 spd->t_pllrst = PLLRST_VAL;
295 spd->t_phyrst = PHYRST_VAL;
303 struct ddr3_sodimm *spd)
305 spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13;
308 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |
309 ((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f);
310 spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |
311 (spd->t_pllrst & 0x1fff);
313 spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) |
314 (spd->t_dinit0 & 0xfffff);
315 spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) |
316 (spd->t_dinit2 & 0x3ffff);
321 if (spd->mirrored) {
326 spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 |
327 (spd->t_rrd & 0xf) << 22 |
328 (spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 |
329 (spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 |
330 (spd->t_rtp & 0xf);
331 spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 |
332 (spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 |
333 (spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 |
334 (spd->t_mrd & 0x3);
337 (spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15;
339 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ?
340 spd->t_xp : spd->t_xpdll) &
343 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ?
344 spd->t_xs : spd->t_xsdll) &
347 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |
348 0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 |
349 (spd->cas & 0x01) << 2;
356 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 |
357 (spd->cwl & 7) << 3 | (spd->pasr & 7);
359 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;
360 spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);
370 spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 |
371 (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 |
372 (spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 |
373 (spd->buswidth & 3) << 12 | (spd->pagesize & 3);
375 if (spd->rank == 2)
378 spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 |
379 ((spd->t_ras - 1) & 0x7f) << 18 |
380 ((spd->t_rc - 1) & 0xff) << 10 |
381 (spd->t_rrd2 & 0x3f) << 4 |
382 ((spd->t_wtr - 1) & 0xf);
384 spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 |
385 ((spd->t_rcd - 1) & 0x1f);
387 spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 |
388 ((spd->t_xs - 1) & 0x3ff) << 18 |
389 ((spd->t_xsdll - 1) & 0x3ff) << 8 |
390 ((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf);
392 spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 |
393 ((spd->t_ckesr - 1) & 0xf) << 24 |
394 ((spd->t_zqcs - 1) & 0xff) << 16 |
395 ((spd->t_rfc - 1) & 0x3ff) << 4 |
396 (spd->t_ras_max & 0xf);
398 spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff;
401 spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200;
435 struct ddr3_sodimm spd;
438 memset(&spd, 0, sizeof(spd));
443 if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) {
451 init_ddr3param(spd_cb, &spd);