mach-imx/mx6/clock.c

288 	u64 freq;
299 		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
303 		freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
310 	return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
316 	u32 reg, freq;
321 	freq = decode_pll(PLL_SYS, MXC_HCLK);
323 	return freq / (reg + 1);
328 	u32 reg, div = 0, freq = 0;
340 			freq = decode_pll(PLL_USBOTG, MXC_HCLK);
344 			freq = MXC_HCLK;
356 			freq = decode_pll(PLL_BUS, MXC_HCLK);
359 			freq = mxc_get_pll_pfd(PLL_BUS, 2);
362 			freq = mxc_get_pll_pfd(PLL_BUS, 0);
366 			freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
373 	return freq / (div + 1);
406 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
412 			freq = MXC_HCLK;
418 	return freq / (uart_podf + 1);
544 	u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
555 					freq = MXC_HCLK;
557 					freq = decode_pll(PLL_USBOTG, MXC_HCLK);
560 					freq = decode_pll(PLL_BUS, MXC_HCLK);
562 					freq = decode_pll(PLL_USBOTG, MXC_HCLK);
570 				freq = decode_pll(PLL_BUS, MXC_HCLK);
573 				freq = mxc_get_pll_pfd(PLL_BUS, 2);
576 				freq = mxc_get_pll_pfd(PLL_BUS, 0);
580 					freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
597 				freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
602 		return freq / (podf + 1) / (per2_clk2_podf + 1);
675  * 'freq' using KHz as unit, see driver/video/mxsfb.c.
677 void mxs_set_lcdclk(u32 base_addr, u32 freq)
688 	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
712 	temp = freq * max_pred * max_postd;
725 				freq *= post_div;
731 			printf("Fail to set rate to %dkhz", freq);
736 	/* Choose the best pred and postd to match freq for lcd */
739 			temp = freq * i * j;
751 		printf("Fail to set rate to %dKHz", freq);
765 	 *freq KHz =  --------------------------------
967 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
975 	if (freq < ENET_25MHZ || freq > ENET_125MHZ)
982 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
988 		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
1377 	u32 freq;
1378 	freq = decode_pll(PLL_SYS, MXC_HCLK);
1379 	printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1380 	freq = decode_pll(PLL_BUS, MXC_HCLK);
1381 	printf("PLL_BUS    %8d MHz\n", freq / 1000000);
1382 	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1383 	printf("PLL_OTG    %8d MHz\n", freq / 1000000);
1384 	freq = decode_pll(PLL_ENET, MXC_HCLK);
1385 	printf("PLL_NET    %8d MHz\n", freq / 1000000);