mach-imx/mx5/clock.c

256 	u32 reg, freq;
259 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
260 	return freq / (reg + 1);
292 	uint32_t freq, reg, div;
294 	freq = get_ahb_clk();
299 	return freq / div;
307 	u32 freq, pred1, pred2, podf;
313 		freq = get_lp_apm();
315 		freq = get_periph_clk();
320 	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
326 	u32 freq = 0;
330 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
333 		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
336 		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
339 		freq = get_lp_apm();
343 	return freq;
351 	unsigned int clk_sel, freq, reg, pred, podf;
355 	freq = get_standard_pll_sel_clk(clk_sel);
360 	freq /= (pred + 1) * (podf + 1);
362 	return freq;
370 	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
377 	freq = get_standard_pll_sel_clk(clk_sel);
378 	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
387 	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
416 	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
417 	return freq;
560 	 * Make sure targeted freq is in the valid range.
707 static int config_core_clk(u32 ref, u32 freq)
715 	ret = calc_pll_params(ref, freq, &pll_param);
766 static int config_periph_clk(u32 ref, u32 freq)
774 		ret = calc_pll_params(ref, freq, &pll_param);
844 static int config_ldb_clk(u32 ref, u32 freq)
851 	ret = calc_pll_params(ref, freq, &pll_param);
861 static int config_ldb_clk(u32 ref, u32 freq)
871  * it is. So it assumes the PLL output freq is the same as the expected
888 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
890 	freq *= SZ_DEC_1M;
894 		if (config_core_clk(ref, freq))
898 		if (config_periph_clk(ref, freq))
902 		if (config_ddr_clk(freq))
906 		if (config_nfc_clk(freq))
910 		if (config_ldb_clk(ref, freq))
951 	u32 freq;
953 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
954 	printf("PLL1       %8d MHz\n", freq / 1000000);
955 	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
956 	printf("PLL2       %8d MHz\n", freq / 1000000);
957 	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
958 	printf("PLL3       %8d MHz\n", freq / 1000000);
960 	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
961 	printf("PLL4       %8d MHz\n", freq / 1000000);