arm/mach-exynos/dmc_init_exynos4.c

27 #include <asm/arch/dmc.h>
51 static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
55 		       &dmc->phycontrol1);
57 		       &dmc->phycontrol1);
60 		       &dmc->phycontrol0);
62 		       &dmc->phycontrol0);
66 static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
76 		       &dmc->directcmd);
80 static void dmc_init(struct exynos4_dmc *dmc)
87 	writel(mem.control1, &dmc->phycontrol1);
94 	writel(mem.zqcontrol, &dmc->phyzqcontrol);
101 	phy_control_reset(1, dmc);
102 	phy_control_reset(0, dmc);
105 	writel(mem.control1, &dmc->phycontrol1);
108 	writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
110 	writel(mem.control2, &dmc->phycontrol2);
113 	writel(mem.concontrol, &dmc->concontrol);
122 	writel(mem.memcontrol, &dmc->memcontrol);
124 	writel(mem.memconfig0, &dmc->memconfig0);
125 	writel(mem.memconfig1, &dmc->memconfig1);
128 	writel(mem.prechconfig, &dmc->prechconfig);
133 	writel(mem.timingref, &dmc->timingref);
134 	writel(mem.timingrow, &dmc->timingrow);
135 	writel(mem.timingdata, &dmc->timingdata);
136 	writel(mem.timingpower, &dmc->timingpower);
139 	writel(DIRECT_CMD_NOP, &dmc->directcmd);
143 	dmc_config_mrs(dmc, 0);
147 	writel(DIRECT_CMD_ZQ, &dmc->directcmd);
150 	writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
154 	dmc_config_mrs(dmc, 1);
158 	writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
161 	phy_control_reset(1, dmc);
165 	writel((mem.concontrol | AREF_EN), &dmc->concontrol);
170 	struct exynos4_dmc *dmc;
208 	dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
209 	dmc_init(dmc);
210 	dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
212 	dmc_init(dmc);