arch-octeontx2/csrs/csrs-nix.h

728  * packets to be transmitted by NIX.
1145  * data bytes. There may be multiple NIX_RX_SG_Ss in each NIX receive
1213  * specifies a CRC calculation be performed during transmission. Ignored
1215  * may be up to two NIX_SEND_CRC_Ss per send descriptor.  NIX_SEND_CRC_S
1222  * NIX_SEND_CRC_S. There must be no overlap between any NIX_SEND_CRC_S
1231  * NIX_SEND_HDR_S[OL3TYPE,OL4TYPE,IL3TYPE,IL4TYPE] must be outside of the
1257  * NIX_SEND_HDR_S. All fields are assumed to be zero when this
1321  * NIX_SEND_IMM_S (after skipping [APAD] bytes) are to be included in the
1324  * the address to a multiple of 16 bytes.  There may be multiple
1329  * descriptor, all NIX_SEND_IMM_S bytes must be included in the first
1350  * can be only one NIX_SEND_JUMP_S subdescriptor in a send descriptor. If
1406  * data bytes to be transmitted. There may be multiple NIX_SEND_SG_Ss in
1441  * must be the last subdescriptor. NIX will not initiate the work add for
1447  * unmodified between the descriptors (as should normally be the case,
1646  * Vtag 0 byte offset from packet start (see [VTAG0_RELPTR]) must be less
1651  * immediately after Vtag 0 in the packet.  A Vtag must not be inserted
1652  * or replaced within an outer or inner L3/L4 header, but may be inserted
2599 		u64 be                               : 1;
2725  * skip bytes). NPC's MCAM can be used for deeper protocol-aware
3372  * eight fields are modified, [ALG] must be NIX_LSOALG_E::NOP in the
3373  * unused field registers. * Modified fields must be specified in
3376  * [LAYER] value must be specified in ascending [OFFSET] order. * Fields
3377  * in different layers must be specified in ascending [LAYER] order.
3694  * not be written during normal operation.
4472  * of RAS events to the SCP, so should be ignored by OS drivers.
6780  * NIX AF Transmit Level 1 Shape State Register This register must not be
7392  * be written during normal operation.
7963  * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be
8126  * on. Each TL3/TL2 queue can be enabled to transmit on and be
8654  * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be
8904  * allows NPC responses for selected packets to be captured in
9616  * NIX_SEND_JUMP_S, and the remainder of the send descriptor must be at
9618  * all LLC/DRAM locations that will be referenced by NIX while processing
9621  * DMB instruction may be required prior to the LMTST to ensure this. A
9622  * DMB following the LMTST may be useful if SQ descriptor ordering
10356  * allow each NIX local function (LF) to be provisioned to a VF/PF for
10360  * must be zero.  Internal: Hardware ignores [SLOT] and always assumes