Lines Matching refs:r1
24 mcr IIALL(r1)
44 mrc SCTLR(r1)
45 and r1, r1, #(1 << 2)
46 cmp r1, #0
51 mrc SCTLR(r1)
52 bic r1, r1, #(1 << 12) /* Disable I-cache */
53 bic r1, r1, #(1 << 2) /* Disable D-Cache */
54 bic r1, r1, #(1 << 0) /* Disable MMU */
55 mcr SCTLR(r1)
63 orr r1, r0, #0x19
64 mcr TTBR0(r1)
65 mcr TLBIALL(r1)
68 mov r1, #1
69 mcr DACR(r1)
72 mov r1, #0
73 mcr CONTEXTIDR(r1) /* set ASID to 0 */
74 mcr TTBCR(r1) /* set TTBCR to 0 */
75 mcr BPIALL(r1) /* flush branch target cache */
99 mrc SCTLR(r1)
100 and r1, r1, #(1 << 2)
101 cmp r1, #0
106 mrc SCTLR(r1)
107 bic r1, r1, #(1 << 2) /* Disable D-Cache */
108 mcr SCTLR(r1)