riscv-pk/machine/emulation.c

15   write_csr(mepc, mepc + 2);
19     return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
24       return misaligned_load_trap(regs, mcause, mepc);
25     SET_F64_RD(RVC_RS2S(insn) << SH_RD, regs, load_uint64_t((void *)addr, mepc));
29       return misaligned_load_trap(regs, mcause, mepc);
30     SET_F64_RD(insn, regs, load_uint64_t((void *)addr, mepc));
34       return misaligned_store_trap(regs, mcause, mepc);
35     store_uint64_t((void *)addr, GET_F64_RS2(RVC_RS2S(insn) << SH_RS2, regs), mepc);
39       return misaligned_store_trap(regs, mcause, mepc);
40     store_uint64_t((void *)addr, GET_F64_RS2(RVC_RS2(insn) << SH_RS2, regs), mepc);
46       return misaligned_load_trap(regs, mcause, mepc);
47     SET_F32_RD(RVC_RS2S(insn) << SH_RD, regs, load_int32_t((void *)addr, mepc));
51       return misaligned_load_trap(regs, mcause, mepc);
52     SET_F32_RD(insn, regs, load_int32_t((void *)addr, mepc));
56       return misaligned_store_trap(regs, mcause, mepc);
57     store_uint32_t((void *)addr, GET_F32_RS2(RVC_RS2S(insn) << SH_RS2, regs), mepc);
61       return misaligned_store_trap(regs, mcause, mepc);
62     store_uint32_t((void *)addr, GET_F32_RS2(RVC_RS2(insn) << SH_RS2, regs), mepc);
68   return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
71 void illegal_insn_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc)
138       insn = get_insn(mepc, &mstatus);
140       return emulate_rvc(regs, mcause, mepc, mstatus, insn);
143   write_csr(mepc, mepc + 4);
148   f(regs, mcause, mepc, mstatus, insn);
154   return redirect_trap(mepc, mstatus, insn);
274     return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
279     case 0: return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
283     case 4: return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
290     return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);