plat/tk1/spi.c

111 struct spi_bus {
137     spi_bus_t* spi_bus = &_spi[id];
138     spi_bus->cs = cs_func;
139     spi_bus->regs = base + spi_controller_offsets[id];
149     spi_bus->regs->fifo_status = fifo_status;
151     uint32_t command1 = spi_bus->regs->command1;
152     command1 |= (spi_bus->clock_mode << SPI_CMD1_MODE_SHIFT);
153     if (spi_bus->cs != NULL) {
159     spi_bus->regs->command1 = command1;
161     uint32_t command2 = spi_bus->regs->command2;
163     spi_bus->regs->command2 = command2;
165     uint32_t timing1 = spi_bus->regs->timing1;
168     spi_bus->regs->timing1 = timing1;
170     uint32_t dma_ctl = spi_bus->regs->dma_ctl;
172     spi_bus->regs->dma_ctl = dma_ctl;
174     spi_bus->regs->xfer_status |= SPI_XFER_STS_RDY;
176     *ret_spi_bus = spi_bus;
181 finish_spi_transfer(spi_bus_t* spi_bus) {
183     size_t size = spi_bus->txsize + spi_bus->rxsize;
185         uint32_t data_in = spi_bus->regs->rx_fifo;
186         if (spi_bus->rxbuf != NULL) {
187             spi_bus->rxbuf[i] = (uint8_t) (data_in & 0xFF);
191     spi_bus->regs->xfer_status |= SPI_XFER_STS_RDY;
192     spi_bus->in_progress = false;
195     if (spi_bus->cs != NULL) {
196         spi_bus->cs(spi_bus->curr_slave, SPI_CS_RELAX);
199     spi_bus->cb(spi_bus, size, spi_bus->token);
203 spi_handle_irq(spi_bus_t* spi_bus)
205     if (spi_bus->regs->xfer_status & SPI_XFER_STS_RDY) {
206         finish_spi_transfer(spi_bus);
208         uint32_t fifo_status = spi_bus->regs->fifo_status;
212         spi_bus->regs->command1 &= ~SPI_CMD1_GO;
215         spi_bus->regs->fifo_status = fifo_status;
217         spi_bus->regs->xfer_status |= SPI_XFER_STS_RDY;
218         spi_bus->in_progress = false;
220         if (spi_bus->cs != NULL) {
221             spi_bus->cs(spi_bus->curr_slave, SPI_CS_RELAX);
224         spi_bus->cb(spi_bus, -1, spi_bus->token);
229 start_spi_transfer(spi_bus_t* spi_bus) {
231     if (spi_bus->cs != NULL) {
232         spi_bus->cs(spi_bus->curr_slave, SPI_CS_ASSERT);
234     size_t size = spi_bus->txsize + spi_bus->rxsize;
235     spi_bus->regs->dma_blk = size - 1;
239         if (i < spi_bus->txsize) {
240             spi_bus->regs->tx_fifo = spi_bus->txbuf[i];
242             spi_bus->regs->tx_fifo = 0;
247     spi_bus->regs->command1 |= SPI_CMD1_GO;
251 spi_xfer(spi_bus_t* spi_bus, const void* txdata, size_t txcnt,
254     if (spi_bus->in_progress) {
267     spi_bus->txbuf = (uint8_t*) txdata;
268     spi_bus->rxbuf = (uint8_t*) rxdata;
269     spi_bus->txsize = txcnt;
270     spi_bus->rxsize = rxcnt;
271     spi_bus->in_progress = true;
272     spi_bus->cb = cb;
273     spi_bus->token = token;
275     start_spi_transfer(spi_bus);
280 spi_prepare_transfer(spi_bus_t* spi_bus, const spi_slave_config_t* cfg)
283     spi_bus->curr_slave = (spi_slave_config_t *)cfg;