Lines Matching refs:word
32 type word = bits(32)
43 Word :: word
501 register FPCSR :: word -- 32-bit control register
1266 st_width :: word option -- width of store (optimization for sub-word store checks)
1294 inline unit recordStore(addr::vAddr, val::regType, width::word) =
1314 string hex32(x::word) = PadLeft(#"0", 8, [x])
1393 string log_w_fprs(r::reg, data::word) =
1621 component FPRS(n::reg) :: word
1635 unit writeFPRS(rd::reg, val::word) =
4239 instruction Decode(w::word) =
4708 word Rtype(o::opcode, f3::bits(3), rd::reg, rs1::reg, rs2::reg, f7::bits(7)) =
4711 word R4type(o::opcode, f3::bits(3), rd::reg, rs1::reg, rs2::reg, rs3::reg, f2::bits(2)) =
4714 word Itype(o::opcode, f3::bits(3), rd::reg, rs1::reg, imm::imm12) =
4717 word Stype(o::opcode, f3::bits(3), rs1::reg, rs2::reg, imm::imm12) =
4720 word SBtype(o::opcode, f3::bits(3), rs1::reg, rs2::reg, imm::imm12) =
4723 word Utype(o::opcode, rd::reg, imm::imm20) =
4726 word UJtype(o::opcode, rd::reg, imm::imm20) =
4734 word Encode(i::instruction) =
5002 construct rvc { Comp :: half, Full :: word }
5206 string log_instruction(w::word, inst::instruction) =
5264 { mark_log(LOG_INSN, log_instruction([0::word], inst))