arm/model/arm.sig

27 type SCTLR =
55     SCR: SCR, SCTLR: SCTLR, VBAR: BitsN.nbit }
469 val SCTLR_A_rupd: SCTLR * bool -> SCTLR
470 val SCTLR_B_rupd: SCTLR * bool -> SCTLR
471 val SCTLR_BR_rupd: SCTLR * bool -> SCTLR
472 val SCTLR_C_rupd: SCTLR * bool -> SCTLR
473 val SCTLR_DZ_rupd: SCTLR * bool -> SCTLR
474 val SCTLR_EE_rupd: SCTLR * bool -> SCTLR
475 val SCTLR_FI_rupd: SCTLR * bool -> SCTLR
476 val SCTLR_I_rupd: SCTLR * bool -> SCTLR
477 val SCTLR_IE_rupd: SCTLR * bool -> SCTLR
478 val SCTLR_M_rupd: SCTLR * bool -> SCTLR
479 val SCTLR_NMFI_rupd: SCTLR * bool -> SCTLR
480 val SCTLR_RR_rupd: SCTLR * bool -> SCTLR
481 val SCTLR_SW_rupd: SCTLR * bool -> SCTLR
482 val SCTLR_TE_rupd: SCTLR * bool -> SCTLR
483 val SCTLR_U_rupd: SCTLR * bool -> SCTLR
484 val SCTLR_V_rupd: SCTLR * bool -> SCTLR
485 val SCTLR_VE_rupd: SCTLR * bool -> SCTLR
486 val SCTLR_Z_rupd: SCTLR * bool -> SCTLR
487 val SCTLR_sctlr'rst_rupd: SCTLR * BitsN.nbit -> SCTLR
549 val CP15_SCTLR_rupd: CP15 * SCTLR -> CP15
629 val rec'SCTLR: BitsN.nbit -> SCTLR
630 val reg'SCTLR: SCTLR -> BitsN.nbit
631 val write'rec'SCTLR: (BitsN.nbit * SCTLR) -> BitsN.nbit
632 val write'reg'SCTLR: (SCTLR * BitsN.nbit) -> SCTLR