Lines Matching refs:pte
1783 ; pte = SV_PTE(rawReadData(pte_addr))
1788 : " pte=0x" : PadLeft(#"0", 16, [&pte])])
1789 ; if not pte.PTE_V
1793 else { if pte.PTE_T == 0 or pte.PTE_T == 1
1799 else walk64(vAddr, ft, ac, priv, ZeroExtend(pte.PTE_PPNi << PAGESIZE_BITS), level - 1)
1802 if not checkMemPermission(ft, ac, priv, pte.PTE_T)
1806 else { var pte_w = pte
1808 ; old_r = pte.PTE_R
1809 ; old_d = pte.PTE_D
1817 then ((ZeroExtend((pte.PTE_PPNi >>+ (level * LEVEL_BITS)) << (level * LEVEL_BITS)))
1819 else pte.PTE_PPNi
1820 ; Some(ZeroExtend(ppn : va.Sv_PgOfs), pte_w, level, isGlobal(pte.PTE_T), pte_addr)
1857 pte :: SV_PTE -- permissions and dirty bit writeback
1864 pte::SV_PTE, i::nat, pteAddr::pAddr) =
1868 ; ent.pte <- pte
1895 TLBMap addToTLB(asid::asidType, vAddr::vAddr, pAddr::pAddr, pte::SV_PTE, pteAddr::pAddr,
1897 { var ent = mkTLBEntry(asid, global, vAddr, pAddr, pte, i, pteAddr)
1947 { if checkMemPermission(ft, ac, priv, e.pte.PTE_T)
1950 ; when ac == Write and not e.pte.PTE_D
1952 ; ent.pte.PTE_D <- true
1953 ; rawWriteData(ent.pteAddr, ent.&pte, 8)
1967 { case Some(pAddr, pte, i, global, pteAddr) =>
1968 { TLB <- addToTLB(asid, vAddr, pAddr, pte, pteAddr, i, global, TLB)