mips/model/mips.sig

609 val rec'Index: BitsN.nbit -> Index
611 val write'rec'Index: (BitsN.nbit * Index) -> BitsN.nbit
613 val rec'Random: BitsN.nbit -> Random
615 val write'rec'Random: (BitsN.nbit * Random) -> BitsN.nbit
617 val rec'Wired: BitsN.nbit -> Wired
619 val write'rec'Wired: (BitsN.nbit * Wired) -> BitsN.nbit
621 val rec'EntryLo: BitsN.nbit -> EntryLo
623 val write'rec'EntryLo: (BitsN.nbit * EntryLo) -> BitsN.nbit
625 val rec'PageMask: BitsN.nbit -> PageMask
627 val write'rec'PageMask: (BitsN.nbit * PageMask) -> BitsN.nbit
629 val rec'EntryHi: BitsN.nbit -> EntryHi
631 val write'rec'EntryHi: (BitsN.nbit * EntryHi) -> BitsN.nbit
633 val rec'StatusRegister: BitsN.nbit -> StatusRegister
635 val write'rec'StatusRegister: (BitsN.nbit * StatusRegister) -> BitsN.nbit
638 val rec'ConfigRegister: BitsN.nbit -> ConfigRegister
640 val write'rec'ConfigRegister: (BitsN.nbit * ConfigRegister) -> BitsN.nbit
643 val rec'ConfigRegister1: BitsN.nbit -> ConfigRegister1
645 val write'rec'ConfigRegister1:
649 val rec'ConfigRegister2: BitsN.nbit -> ConfigRegister2
651 val write'rec'ConfigRegister2:
655 val rec'ConfigRegister3: BitsN.nbit -> ConfigRegister3
657 val write'rec'ConfigRegister3:
661 val rec'ConfigRegister6: BitsN.nbit -> ConfigRegister6
663 val write'rec'ConfigRegister6:
667 val rec'CauseRegister: BitsN.nbit -> CauseRegister
669 val write'rec'CauseRegister: (BitsN.nbit * CauseRegister) -> BitsN.nbit
671 val rec'Context: BitsN.nbit -> Context
673 val write'rec'Context: (BitsN.nbit * Context) -> BitsN.nbit
675 val rec'XContext: BitsN.nbit -> XContext
677 val write'rec'XContext: (BitsN.nbit * XContext) -> BitsN.nbit
679 val rec'HWREna: BitsN.nbit -> HWREna
681 val write'rec'HWREna: (BitsN.nbit * HWREna) -> BitsN.nbit
729 val rec'FCSR: BitsN.nbit -> FCSR
731 val write'rec'FCSR: (BitsN.nbit * FCSR) -> BitsN.nbit
733 val rec'FIR: BitsN.nbit -> FIR
735 val write'rec'FIR: (BitsN.nbit * FIR) -> BitsN.nbit