l3-machine-code/cheri/cheriScript.sml

446 val raise'exception_def = Def
456 val rec'EntryLo_def = Def
464 val reg'EntryLo_def = Def
474 val write'rec'EntryLo_def = Def
478 val write'reg'EntryLo_def = Def
482 val rec'Index_def = Def
488 val reg'Index_def = Def
495 val write'rec'Index_def = Def
499 val write'reg'Index_def = Def
503 val rec'Random_def = Def
508 val reg'Random_def = Def
514 val write'rec'Random_def = Def
518 val write'reg'Random_def = Def
522 val rec'Wired_def = Def
527 val reg'Wired_def = Def
533 val write'rec'Wired_def = Def
537 val write'reg'Wired_def = Def
541 val rec'PageMask_def = Def
548 val reg'PageMask_def = Def
556 val write'rec'PageMask_def = Def
560 val write'reg'PageMask_def = Def
564 val rec'EntryHi_def = Def
572 val reg'EntryHi_def = Def
582 val write'rec'EntryHi_def = Def
586 val write'reg'EntryHi_def = Def
590 val rec'StatusRegister_def = Def
605 val reg'StatusRegister_def = Def
624 val write'rec'StatusRegister_def = Def
628 val write'reg'StatusRegister_def = Def
632 val rec'ConfigRegister_def = Def
642 val reg'ConfigRegister_def = Def
655 val write'rec'ConfigRegister_def = Def
659 val write'reg'ConfigRegister_def = Def
663 val rec'ConfigRegister1_def = Def
676 val reg'ConfigRegister1_def = Def
691 val write'rec'ConfigRegister1_def = Def
695 val write'reg'ConfigRegister1_def = Def
700 val rec'ConfigRegister2_def = Def
709 val reg'ConfigRegister2_def = Def
719 val write'rec'ConfigRegister2_def = Def
723 val write'reg'ConfigRegister2_def = Def
728 val rec'ConfigRegister3_def = Def
740 val reg'ConfigRegister3_def = Def
759 val write'rec'ConfigRegister3_def = Def
763 val write'reg'ConfigRegister3_def = Def
768 val rec'ConfigRegister6_def = Def
775 val reg'ConfigRegister6_def = Def
786 val write'rec'ConfigRegister6_def = Def
790 val write'reg'ConfigRegister6_def = Def
795 val rec'CauseRegister_def = Def
804 val reg'CauseRegister_def = Def
817 val write'rec'CauseRegister_def = Def
821 val write'reg'CauseRegister_def = Def
825 val rec'Context_def = Def
831 val reg'Context_def = Def
840 val write'rec'Context_def = Def
844 val write'reg'Context_def = Def
848 val rec'XContext_def = Def
855 val reg'XContext_def = Def
864 val write'rec'XContext_def = Def
868 val write'reg'XContext_def = Def
872 val rec'HWREna_def = Def
883 val reg'HWREna_def = Def
897 val write'rec'HWREna_def = Def
901 val write'reg'HWREna_def = Def
913 val println_def = Def ("println",sVar"s",Close(qVar"state",LU))
915 val cpr_def = Def
933 val hex_def = Def
944 val log_sig_exception_def = Def
948 val log_w_gpr_def = Def
953 val log_w_hi_def = Def
957 val log_w_lo_def = Def
961 val log_w_c0_def = Def
966 val log_w_mem_def = Def
972 val log_r_mem_def = Def
981 val gpr_def = Def
987 val write'gpr_def = Def
998 val GPR_def = Def
1005 val write'GPR_def = Def
1016 val PC_def = Def
1020 val write'PC_def = Def
1032 val hi_def = Def
1036 val write'hi_def = Def
1048 val lo_def = Def
1052 val write'lo_def = Def
1064 val CP0_def = Def
1068 val write'CP0_def = Def
1080 val BranchDelay_def = Def
1085 val write'BranchDelay_def = Def
1097 val BranchTo_def = Def
1101 val write'BranchTo_def = Def
1113 val LLbit_def = Def
1117 val write'LLbit_def = Def
1129 val exceptionSignalled_def = Def
1135 val write'exceptionSignalled_def = Def
1146 val UserMode_def = Def
1168 val SupervisorMode_def = Def
1190 val KernelMode_def = Def
1211 val BigEndianMem_def = Def
1219 val ReverseEndian_def = Def
1230 val BigEndianCPU_def = Def
1236 val NotWordValue_def = Def
1242 val CheckBranch_def = Def
1254 val dumpRegs_def = Def ("dumpRegs",AVar uTy,LU)
1256 val coreStats_def = Def
1262 val write'coreStats_def = Def
1274 val initCoreStats_def = Def
1294 val printCoreStats_def = Def
1318 val csvCoreStats_def = Def
1330 val next_unknown_def = Def
1350 val rec'UPerms_def = Def
1355 val reg'UPerms_def = Def
1361 val write'rec'UPerms_def = Def
1365 val write'reg'UPerms_def = Def
1369 val rec'Perms_def = Def
1380 val reg'Perms_def = Def
1399 val write'rec'Perms_def = Def
1403 val write'reg'Perms_def = Def
1407 val rec'Capability_def = Def
1419 val reg'Capability_def = Def
1430 val write'rec'Capability_def = Def
1434 val write'reg'Capability_def = Def
1490 val canRepOffset_def = Def
1493 val canRepSeal_def = Def
1496 val canRepBounds_def = Def
1499 val getTag_def = Def
1503 val getType_def = Def
1507 val getPerms_def = Def
1513 val getUPerms_def = Def
1519 val getSealed_def = Def
1523 val getOffset_def = Def
1528 val getBase_def = Def
1532 val getLength_def = Def
1536 val getBaseAndLength_def = Def
1541 val setTag_def = Def
1545 val setType_def = Def
1549 val setPerms_def = Def
1557 val setUPerms_def = Def
1565 val setSealed_def = Def
1569 val setOffset_def = Def
1577 val setBounds_def = Def
1587 val log_cap_write_def = Def
1606 val log_cpp_write_def = Def
1610 val log_creg_write_def = Def
1615 val log_store_cap_def = Def
1620 val log_load_cap_def = Def
1625 val isCapAligned_def = Def
1629 val capToBits_def = Def
1634 val bitsToCap_def = Def
1638 val readDwordFromRaw_def = Def
1646 val updateDwordInRaw_def = Def
1678 val rec'CapCause_def = Def
1683 val reg'CapCause_def = Def
1689 val write'rec'CapCause_def = Def
1693 val write'reg'CapCause_def = Def
1697 val switchCoreCAP_def = Def
1857 val dumpCRegs_def = Def ("dumpCRegs",AVar uTy,LU)
1859 val PCC_def = Def
1862 val write'PCC_def = Def
1868 val CAPR_def = Def
1876 val write'CAPR_def = Def
1887 val RCC_def = Def
1891 val write'RCC_def = Def
1900 val IDC_def = Def
1904 val write'IDC_def = Def
1913 val KR1C_def = Def
1917 val write'KR1C_def = Def
1926 val KR2C_def = Def
1930 val write'KR2C_def = Def
1939 val KCC_def = Def
1943 val write'KCC_def = Def
1952 val KDC_def = Def
1956 val write'KDC_def = Def
1965 val EPCC_def = Def
1969 val write'EPCC_def = Def
1978 val allow_system_reg_access_def = Def
1990 val ExceptionCode_def = Def
2012 val capExcCode_def = Def
2037 val SignalException_def = Def
2339 val SignalCP1UnusableException_def = Def
2358 val SignalCP2UnusableException_def = Def
2377 val SignalCapException_internal_def = Def
2404 val SignalCapException_def = Def
2415 val SignalCapException_noReg_def = Def
2425 val dfn'ERET_def = Def
2524 val TLB_direct_def = Def
2532 val write'TLB_direct_def = Def
2543 val TLB_assoc_def = Def
2551 val write'TLB_assoc_def = Def
2562 val switchCoreTLB_def = Def
2606 val LookupTLB_def = Def
2795 val SignalTLBException_internal_def = Def
2928 val SignalTLBException_def = Def
2950 val CheckSegment_def = Def
3003 val checkMask_def = Def
3011 val check_cca_def = Def
3025 val AddressTranslation_def = Def
3071 val tlbTryTranslation_def = Def
3074 val CP0TLBEntry_def = Def
3087 val SignalTLBCapException_def = Def
3107 val dfn'TLBP_def = Def
3215 val dfn'TLBR_def = Def
3649 val dfn'TLBWI_def = Def
3729 val dfn'TLBWR_def = Def
3814 val reg_name_def = Def
3830 val ihex_def = Def
3835 val op1i_def = Def
3840 val op1ai_def = Def
3845 val op1lai_def = Def
3852 val op1r_def = Def
3857 val op1ri_def = Def
3862 val op1rai_def = Def
3867 val op1rlai_def = Def
3874 val op2r_def = Def
3879 val op2ri_def = Def
3884 val op2rai_def = Def
3889 val op2rlai_def = Def
3896 val op3r_def = Def
3901 val op2roi_def = Def
3908 val opmem_def = Def
3913 val op1fpr_def = Def
3918 val op1fpri_def = Def
3923 val op2fpr_def = Def
3928 val op2rfpr_def = Def
3933 val op2rcfpr_def = Def
3938 val op2ccfpr_def = Def
3946 val op3fpr_def = Def
3951 val op4fpr_def = Def
3960 val opfpmem_def = Def
3965 val opfpmem2_def = Def
3971 val form1_def = Def
3978 val form2_def = Def
3982 val form3_def = Def
3989 val form4_def = Def
3994 val form5_def = Def
4001 val form6_def = Def
4022 val isAligned_def = Def
4027 val AdjustEndian_def = Def
4060 val InitMEM_def = Def
4075 val ReadData_def = Def
4093 val WriteData_def = Def
4128 val ReadInst_def = Def
4151 val ReadCap_def = Def
4163 val WriteCap_def = Def
4175 val WriteDWORD_def = Def
4210 val Write256_def = Def
4222 val getVirtualAddress_def = Def
4238 val LoadMemoryCap_def = Def
4301 val LoadMemory_def = Def
4406 val LoadCap_def = Def
4433 val StoreMemoryCap_def = Def
4620 val StoreMemory_def = Def
4728 val StoreCap_def = Def
4907 val Fetch_def = Def
5211 val switchCore_def = Def
5272 val resetStats_def = Def
5276 val dumpStats_def = Def
5279 val clearDynamicStats_def = Def ("clearDynamicStats",AVar uTy,LU)
5281 val HI_def = Def
5294 val write'HI_def = Def
5302 val LO_def = Def
5315 val write'LO_def = Def
5323 val CPR_def = Def
5543 val write'CPR_def = Def
5998 val log_w_fgr_def = Def
6003 val rec'FCSR_def = Def
6020 val reg'FCSR_def = Def
6043 val write'rec'FCSR_def = Def
6047 val write'reg'FCSR_def = Def
6051 val rec'FIR_def = Def
6060 val reg'FIR_def = Def
6072 val write'rec'FIR_def = Def
6076 val write'reg'FIR_def = Def
6080 val FGR_def = Def
6086 val write'FGR_def = Def
6097 val IntToWordMIPS_def = Def
6103 val IntToDWordMIPS_def = Def
6109 val FP32_Abs1985_def = Def
6114 val FP32_Neg1985_def = Def
6119 val FP64_Abs1985_def = Def
6124 val FP64_Neg1985_def = Def
6129 val PostOpF32_def = Def
6136 val PostOpF64_def = Def
6143 val FP64_Unordered_def = Def
6147 val FP32_Unordered_def = Def
6151 val Rounding_Mode_def = Def
6159 val dfn'ABS_D_def = Def
6193 val dfn'ABS_S_def = Def
6233 val dfn'ADD_D_def = Def
6265 val dfn'ADD_S_def = Def
6300 val dfn'BC1F_def = Def
6328 val dfn'BC1FL_def = Def
6363 val dfn'BC1T_def = Def
6390 val dfn'BC1TL_def = Def
6424 val dfn'C_cond_D_def = Def
6553 val dfn'C_cond_S_def = Def
6693 val dfn'CEIL_L_D_def = Def
6718 val dfn'CEIL_L_S_def = Def
6744 val dfn'CEIL_W_D_def = Def
6769 val dfn'CEIL_W_S_def = Def
6795 val dfn'CVT_D_L_def = Def
6820 val dfn'CVT_D_S_def = Def
6841 val dfn'CVT_D_W_def = Def
6883 val dfn'CVT_L_D_def = Def
6910 val dfn'CVT_L_S_def = Def
6938 val dfn'CVT_S_D_def = Def
6963 val dfn'CVT_S_L_def = Def
6990 val dfn'CVT_S_W_def = Def
7033 val dfn'CVT_W_D_def = Def
7060 val dfn'CVT_W_S_def = Def
7088 val dfn'DIV_D_def = Def
7120 val dfn'DIV_S_def = Def
7155 val dfn'FLOOR_L_D_def = Def
7180 val dfn'FLOOR_L_S_def = Def
7206 val dfn'FLOOR_W_D_def = Def
7231 val dfn'FLOOR_W_S_def = Def
7257 val dfn'LDC1_def = Def
7292 val dfn'LDXC1_def = Def
7331 val dfn'LWC1_def = Def
7380 val dfn'LWXC1_def = Def
7432 val dfn'MADD_D_def = Def
7481 val dfn'MADD_S_def = Def
7536 val dfn'MOV_D_def = Def
7555 val dfn'MOV_S_def = Def
7576 val dfn'MOVF_def = Def
7600 val dfn'MOVF_D_def = Def
7624 val dfn'MOVF_S_def = Def
7649 val dfn'MOVN_D_def = Def
7674 val dfn'MOVN_S_def = Def
7700 val dfn'MOVT_def = Def
7723 val dfn'MOVT_D_def = Def
7746 val dfn'MOVT_S_def = Def
7770 val dfn'MOVZ_D_def = Def
7793 val dfn'MOVZ_S_def = Def
7817 val dfn'MSUB_D_def = Def
7866 val dfn'MSUB_S_def = Def
7921 val dfn'MUL_D_def = Def
7953 val dfn'MUL_S_def = Def
7988 val dfn'NEG_D_def = Def
8022 val dfn'NEG_S_def = Def
8062 val dfn'ROUND_L_D_def = Def
8087 val dfn'ROUND_L_S_def = Def
8113 val dfn'ROUND_W_D_def = Def
8138 val dfn'ROUND_W_S_def = Def
8164 val dfn'SDC1_def = Def
8195 val dfn'SDXC1_def = Def
8230 val dfn'SQRT_D_def = Def
8258 val dfn'SQRT_S_def = Def
8288 val dfn'SUB_D_def = Def
8320 val dfn'SUB_S_def = Def
8355 val dfn'SWC1_def = Def
8395 val dfn'SWXC1_def = Def
8438 val dfn'TRUNC_L_D_def = Def
8463 val dfn'TRUNC_L_S_def = Def
8489 val dfn'TRUNC_W_D_def = Def
8514 val dfn'TRUNC_W_S_def = Def
8540 val dfn'DMFC1_def = Def
8559 val dfn'DMTC1_def = Def
8578 val dfn'MFC1_def = Def
8599 val dfn'MTC1_def = Def
8620 val dfn'CFC1_def = Def
8665 val dfn'CTC1_def = Def
8718 val dfn'UnknownFPInstruction_def = Def
8732 val register_inaccessible_def = Def
8746 val register_inaccessible_write_attempt_def = Def
8815 val watchOOB_def = Def
8819 val SignExtendBitString_def = Def
8823 val ZeroExtendBitString_def = Def
8829 val dfn'CGetBase_def = Def
8861 val dfn'CGetOffset_def = Def
8893 val dfn'CGetLen_def = Def
8925 val dfn'CGetTag_def = Def
8959 val dfn'CGetSealed_def = Def
9007 val dfn'CGetPerm_def = Def
9053 val dfn'CGetType_def = Def
9095 val dfn'CGetPCC_def = Def
9127 val dfn'CGetPCCSetOffset_def = Def
9184 val dfn'CGetCause_def = Def
9246 val dfn'CSetCause_def = Def
9291 val dfn'CIncOffset_def = Def
9407 val dfn'CIncOffsetImmediate_def = Def
9513 val dfn'CSetBounds_def = Def
9629 val dfn'CSetBoundsExact_def = Def
9761 val dfn'CSetBoundsImmediate_def = Def
9872 val dfn'CClearRegs_def = Def
9976 val dfn'CClearTag_def = Def
10016 val dfn'CAndPerm_def = Def
10124 val dfn'CSetOffset_def = Def
10211 val dfn'CSub_def = Def
10272 val dfn'CCheckPerm_def = Def
10362 val dfn'CCheckType_def = Def
10458 val dfn'CFromPtr_def = Def
10556 val dfn'CToPtr_def = Def
10632 val dfn'CPtrCmp_def = Def
10939 val dfn'CBTU_def = Def
10983 val dfn'CBTS_def = Def
11026 val dfn'CSC_def = Def
11203 val dfn'CLC_def = Def
11357 val dfn'CLoad_def = Def
11688 val dfn'CStore_def = Def
11955 val dfn'CLLC_def = Def
12097 val dfn'CLLx_def = Def
12292 val dfn'CSCC_def = Def
12475 val dfn'CSCx_def = Def
12613 val dfn'CMOVN_def = Def
12655 val dfn'CMOVZ_def = Def
12695 val dfn'CJR_def = Def
12839 val dfn'CJALR_def = Def
13014 val dfn'CSeal_def = Def
13186 val dfn'CUnseal_def = Def
13371 val dfn'CCall0_def = Def
13516 val dfn'CCall1_def = Def
13731 val dfn'CReturn_def = Def
13745 val dfn'UnknownCapInstruction_def = Def
13759 val dfn'ADDI_def = Def
13796 val dfn'ADDIU_def = Def
13825 val dfn'DADDI_def = Def
13848 val dfn'DADDIU_def = Def
13861 val dfn'SLTI_def = Def
13875 val dfn'SLTIU_def = Def
13889 val dfn'ANDI_def = Def
13902 val dfn'ORI_def = Def
13915 val dfn'XORI_def = Def
13928 val dfn'LUI_def = Def
13938 val dfn'ADD_def = Def
13983 val dfn'ADDU_def = Def
14020 val dfn'SUB_def = Def
14065 val dfn'SUBU_def = Def
14102 val dfn'DADD_def = Def
14127 val dfn'DADDU_def = Def
14141 val dfn'DSUB_def = Def
14166 val dfn'DSUBU_def = Def
14180 val dfn'SLT_def = Def
14196 val dfn'SLTU_def = Def
14212 val dfn'AND_def = Def
14226 val dfn'OR_def = Def
14240 val dfn'XOR_def = Def
14254 val dfn'NOR_def = Def
14270 val dfn'MOVN_def = Def
14285 val dfn'MOVZ_def = Def
14298 val dfn'MADD_def = Def
14354 val dfn'MADDU_def = Def
14410 val dfn'MSUB_def = Def
14466 val dfn'MSUBU_def = Def
14522 val dfn'MUL_def = Def
14564 val dfn'MULT_def = Def
14607 val dfn'MULTU_def = Def
14650 val dfn'DMULT_def = Def
14671 val dfn'DMULTU_def = Def
14692 val dfn'DIV_def = Def
14731 val dfn'DIVU_def = Def
14770 val dfn'DDIV_def = Def
14793 val dfn'DDIVU_def = Def
14816 val dfn'MFHI_def = Def
14827 val dfn'MFLO_def = Def
14838 val dfn'MTHI_def = Def
14848 val dfn'MTLO_def = Def
14858 val dfn'SLL_def = Def
14873 val dfn'SRL_def = Def
14902 val dfn'SRA_def = Def
14931 val dfn'SLLV_def = Def
14949 val dfn'SRLV_def = Def
14981 val dfn'SRAV_def = Def
15013 val dfn'DSLL_def = Def
15026 val dfn'DSRL_def = Def
15039 val dfn'DSRA_def = Def
15052 val dfn'DSLLV_def = Def
15068 val dfn'DSRLV_def = Def
15084 val dfn'DSRAV_def = Def
15100 val dfn'DSLL32_def = Def
15113 val dfn'DSRL32_def = Def
15126 val dfn'DSRA32_def = Def
15139 val dfn'TGE_def = Def
15151 val dfn'TGEU_def = Def
15163 val dfn'TLT_def = Def
15175 val dfn'TLTU_def = Def
15187 val dfn'TEQ_def = Def
15198 val dfn'TNE_def = Def
15212 val dfn'TGEI_def = Def
15224 val dfn'TGEIU_def = Def
15236 val dfn'TLTI_def = Def
15248 val dfn'TLTIU_def = Def
15260 val dfn'TEQI_def = Def
15271 val dfn'TNEI_def = Def
15284 val loadByte_def = Def
15326 val loadHalf_def = Def
15368 val loadWord_def = Def
15411 val loadDoubleword_def = Def
15436 val dfn'LB_def = Def
15446 val dfn'LBU_def = Def
15456 val dfn'LH_def = Def
15466 val dfn'LHU_def = Def
15476 val dfn'LW_def = Def
15486 val dfn'LWU_def = Def
15496 val dfn'LL_def = Def
15506 val dfn'LD_def = Def
15516 val dfn'LLD_def = Def
15526 val dfn'LWL_def = Def
15612 val dfn'LWR_def = Def
15705 val dfn'LDL_def = Def
15790 val dfn'LDR_def = Def
15884 val dfn'SB_def = Def
15916 val dfn'SH_def = Def
15949 val storeWord_def = Def
15978 val storeDoubleword_def = Def
15997 val dfn'SW_def = Def
16008 val dfn'SD_def = Def
16019 val dfn'SC_def = Def
16037 val dfn'SCD_def = Def
16055 val dfn'SWL_def = Def
16121 val dfn'SWR_def = Def
16221 val dfn'SDL_def = Def
16304 val dfn'SDR_def = Def
16399 val dfn'SYNC_def = Def ("dfn'SYNC",Var("stype",FTy 5),LU)
16401 val dfn'BREAK_def = Def
16407 val dfn'SYSCALL_def = Def
16413 val dfn'MTC0_def = Def
16435 val dfn'DMTC0_def = Def
16457 val dfn'MFC0_def = Def
16483 val dfn'DMFC0_def = Def
16508 val dfn'J_def = Def
16520 val dfn'JAL_def = Def
16540 val dfn'JALR_def = Def
16556 val dfn'JR_def = Def
16568 val dfn'BEQ_def = Def
16586 val dfn'BNE_def = Def
16607 val dfn'BLEZ_def = Def
16626 val dfn'BGTZ_def = Def
16645 val dfn'BLTZ_def = Def
16664 val dfn'BGEZ_def = Def
16683 val dfn'BLTZAL_def = Def
16708 val dfn'BGEZAL_def = Def
16733 val dfn'BEQL_def = Def
16758 val dfn'BNEL_def = Def
16786 val dfn'BLEZL_def = Def
16812 val dfn'BGTZL_def = Def
16838 val dfn'BLTZL_def = Def
16864 val dfn'BGEZL_def = Def
16890 val dfn'BLTZALL_def = Def
16923 val dfn'BGEZALL_def = Def
16956 val dfn'RDHWR_def = Def
17028 val dfn'CACHE_def = Def
17057 val dfn'ReservedInstruction_def = Def
17063 val dfn'Unpredictable_def = Def
17073 val Run_def = Def
18613 val COP1Decode_def = Def
19796 val LDC1Decode_def = Def
19804 val LWC1Decode_def = Def
19812 val SDC1Decode_def = Def
19820 val SWC1Decode_def = Def
19828 val MOVCIDecode_def = Def
19852 val COP3Decode_def = Def
20003 val COP2Decode_def = Def
20850 val LWC2Decode_def = Def
20899 val SWC2Decode_def = Def
20921 val LDC2Decode_def = Def
20931 val SDC2Decode_def = Def
20941 val Decode_def = Def
24881 val COP1InstructionToString_def = Def
25419 val COP1Encode_def = Def
25422 val gr_def = Def
25426 val cr_def = Def
25430 val imm_def = Def
25435 val op_cr_def = Def
25440 val op_gr_def = Def
25445 val op_gr_imm_def = Def
25451 val op_cr_imm_def = Def
25457 val op_cr_gr_def = Def
25463 val op_gr_cr_def = Def
25469 val op_cr_cr_def = Def
25475 val op_cr_cr_gr_def = Def
25483 val op_cr_cr_imm_def = Def
25491 val op_cr_cr_cr_def = Def
25499 val op_gr_cr_cr_def = Def
25507 val op_gr_cr_gr_imm_def = Def
25517 val op_cr_cr_gr_imm_def = Def
25527 val op_gr_gr_cr_def = Def
25535 val COP2InstructionToString_def = Def
25920 val LWC2InstructionToString_def = Def
25979 val LDC2InstructionToString_def = Def
25996 val SWC2InstructionToString_def = Def
26030 val SDC2InstructionToString_def = Def
26047 val CHERICOP2Encode_def = Def
26285 val COP2Encode_def = Def
26308 val LWC2Encode_def = Def
26362 val LDC2Encode_def = Def
26386 val SWC2Encode_def = Def
26410 val SDC2Encode_def = Def
26434 val instructionToString_def = Def
27236 val Encode_def = Def
28257 val COP1Init_def = Def
28559 val log_instruction_def = Def
28578 val Next_def = Def
28762 val COP2Init_def = Def