Lines Matching defs:shift

1799   (size,(regsize_word,(memop,(signed,(m,(extend_type,(shift,(n,t)))))))) =
1801 val offset = ExtendReg 64 (m,(extend_type,shift))
2194 (size,(regsize_word,(memop,(signed,(m,(extend_type,(shift,(n,t)))))))) =
2197 (regsize_word,(memop,(signed,(m,(extend_type,(shift,(n,t)))))))
2607 (shift'1,
2608 (shift'0,
2639 (DecodeShift(BitsN.fromBitstring([shift'1,shift'0],2)),
2653 (shift'1,
2654 (shift'0,
2678 (DecodeShift(BitsN.fromBitstring([shift'1,shift'0],2)),
2811 (shift'1,
2812 (shift'0,
2835 if (BitsN.fromBitstring([shift'1,shift'0],2)) = (BitsN.B(0x0,2))
2858 (shift'1,
2859 (shift'0,
2882 if (BitsN.fromBitstring([shift'1,shift'0],2)) = (BitsN.B(0x0,2))
2977 (shift'1,
2978 (shift'0,
3015 (BitsN.fromBitstring([shift'1,shift'0],2)),
3033 (shift'1,
3034 (shift'0,
3062 (DecodeShift(BitsN.fromBitstring([shift'1,shift'0],2)),
5023 val shift =
5042 (shift,
6441 (size,(regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =
6455 BitsN.fromBit(not(shift = 0)),BitsN.B(0x2,2),rn,rt])
6523 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
6526 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt))))))))
6529 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
6532 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt))))))))
6535 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
6538 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt))))))))
6541 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
6544 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt))))))))
7145 Option.SOME(extend_type,shift) =>
7146 Option.SOME(xn,(rm,(extend_type,shift)))
7271 (xn,(rm,(extend_type,shift))) =>
7279 (shift,(xn,rt)))))))
9507 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
9531 then if shift = 0 then "" else ", lsl " ^ (s_nat shift)
9533 [", ",s_extend_type extend_type," ",s_nat shift],
9538 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
9562 then if shift = 0 then "" else ", lsl " ^ (s_nat shift)
9564 [", ",s_extend_type extend_type," ",s_nat shift],
9569 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
9593 then if shift = 0 then "" else ", lsl " ^ (s_nat shift)
9595 [", ",s_extend_type extend_type," ",s_nat shift],
9600 (regsize_word,(memop,(signed,(rm,(extend_type,(shift,(rn,rt)))))))) =>
9624 then if shift = 0 then "" else ", lsl " ^ (s_nat shift)
9626 [", ",s_extend_type extend_type," ",s_nat shift],