Lines Matching defs:rn
30 ``\opc setflags rn rd mode1.
31 DataProcessing (Data_Processing opc setflags rn rd mode1)``);
255 (let rn = r 16 in
256 if rn = 15w then
257 DataProcessing (Add_Sub F rn (r 12) (i12 0))
259 DP 0b0010w F rn (r 12) (IMM (i12 0)))
261 (let rn = r 16 in
262 if rn = 15w then
263 DataProcessing (Add_Sub T rn (r 12) (i12 0))
265 DP 0b0100w F rn (r 12) (IMM (i12 0)))
559 (let rn = r 8 in
560 let wback = ~(ireg ' (w2n rn)) in
561 LoadStore (Load_Multiple F T F wback rn ((7 >< 0) ireg)))
723 let S = a 4 and rn = ra 0 and rd = rb 8
729 DP 0b1000w T rn 0w (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
733 DP 0b0000w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0)))
735 DP 0b1110w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
737 DP (if rn = 15w then 0b1101w else 0b1100w) S rn rd
740 DP 0b1111w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
744 DP 0b1001w T rn 0w (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
748 DP 0b0001w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0)))
754 (Pack_Halfword rn rd (ib3 12 @@ ib2 6) (b 5) (rb 0)))
758 DP 0b1011w T rn 0w (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
762 DP 0b0100w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0)))
764 DP 0b0101w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
766 DP 0b0110w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
770 DP 0b1010w T rn 0w (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
774 DP 0b0010w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0)))
776 DP 0b0011w S rn rd (REG (ib3 12 @@ ib2 6) (ib2 4) (rb 0))
837 let S = a 4 and rn = ra 0 and rd = rb 8
843 DP 0b1000w T rn 0w (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
847 DP 0b0000w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
849 DP 0b1110w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
851 DP (if rn = 15w then 0b1101w else 0b1100w) S rn rd
854 DP 0b1111w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
858 DP 0b1001w T rn 0w (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
862 DP 0b0001w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
866 DP 0b1011w T rn 0w (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
870 DP 0b0100w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
872 DP 0b0101w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
874 DP 0b0110w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
878 DP 0b1010w T rn 0w (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
882 DP 0b0010w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
884 DP 0b0011w S rn rd (IMM (ia1 10 @@ ib3 12 @@ ib8 0))
1019 let rn = ra 0 and rt = rb 12
1023 if rn = 15w then
1027 (Preload_Data a7 F rn (Mode2_immediate (ib12 0)))
1035 (Load T a7 F F F rn rt (Mode2_immediate (ib12 0)))
1038 (Preload_Instruction a7 rn (Mode2_immediate (ib12 0)))
1046 (Preload_Data T a5 rn (Mode2_immediate (ib12 0)))
1049 (Preload_Data T a5 rn (Mode2_immediate ((7 >< 0) ireg2)))
1052 (Preload_Data T a5 rn
1062 LoadStore (Load T T F F F rn rt (Mode2_immediate (ib12 0)))
1068 (Load b10 b9 F T F rn rt
1075 (Load T b9 F F b9 rn rt (Mode2_immediate ((7 >< 0) ireg2)))
1081 (Load T T F F F rn rt
1085 (Preload_Instruction F rn
1089 (Preload_Instruction F rn (Mode2_immediate (ib12 0)))
1102 if rn = 15w then
1106 (Load T a7 (~a6) F F rn rt (Mode2_immediate (ib12 0)))
1109 (Load_Halfword T a7 F F T F rn rt (Mode3_immediate (ib12 0)))
1112 (Load_Halfword T a7 F T a5 F rn rt
1118 LoadStore (Load T T (~a6) F F rn rt (Mode2_immediate (ib12 0)))
1121 (Load b10 b9 (~a6) T F rn rt
1125 (Load T b9 (~a6) F b9 rn rt
1129 (Load T T (~a6) F F rn rt
1133 (Load_Halfword T T F F T F rn rt (Mode3_immediate (ib12 0)))
1136 (Load_Halfword b10 b9 T F T F rn rt
1140 (Load_Halfword T b9 F F T b9 rn rt
1144 (Load_Halfword T T F F T F rn rt
1148 (Load_Halfword T T F T a5 F rn rt (Mode3_immediate (ib12 0)))
1151 (Load_Halfword b10 b9 T T a5 F rn rt
1155 (Load_Halfword T b9 F T a5 b9 rn rt
1159 (Load_Halfword T T F T a5 F rn rt
1163 if rn = 15w then
1168 LoadStore (Store T T (~a6) F F rn rt (Mode2_immediate (ib12 0)))
1173 (Store b10 b9 (~a6) b8 (b10 /\ b9 /\ ~b8) rn rt
1180 (Store T T (~a6) F F rn rt
1186 (Store_Halfword T T F F rn rt (Mode3_immediate (ib12 0)))
1191 (Store_Halfword b10 b9 b8 (b10 /\ b9 /\ ~b8) rn rt
1198 (Store_Halfword T T F F rn rt