Lines Matching refs:P_PUSHPULL
65 #define P_PUSHPULL BIT(6)
66 #define P_BOTH (P_IN | P_PUSHPULL)
144 PINMAP_2PIN(MUX_FEATURE_UARTA, GPIO_PT0, MUX_PAD_UART1_TX_PT0, 0, P_PUSHPULL,
146 PINMAP_4PIN(MUX_FEATURE_UARTB, GPIO_PX0, MUX_PAD_UART2_TX_PX0, 0, P_PUSHPULL,
148 GPIO_PX2, MUX_PAD_UART2_RTS_PX2, 0, P_PUSHPULL,
150 PINMAP_4PIN(MUX_FEATURE_UARTD, GPIO_PB0, MUX_PAD_UART4_TX_PB0, 0, P_PUSHPULL,
152 GPIO_PB2, MUX_PAD_UART4_RTS_PB2, 0, P_PUSHPULL,
155 PINMAP_4PIN(MUX_FEATURE_SPI1, GPIO_PH0, MUX_PAD_GPIO_WAN5_PH0, 2, P_PUSHPULL,
157 GPIO_PH2, MUX_PAD_GPIO_WAN7_PH2, 2, P_PUSHPULL,
164 PINMAP_4PIN(MUX_FEATURE_SPI4, GPIO_PN3, MUX_PAD_GPIO_CAM4_PN3, 1, P_PUSHPULL,
166 GPIO_PN5, MUX_PAD_GPIO_CAM6_PN5, 1, P_PUSHPULL,
185 PINMAP_6PIN(MUX_FEATURE_EQOS_TX, GPIO_PE0, MUX_PAD_EQOS_TXC_PE0, 0, P_PUSHPULL,
186 GPIO_PE1, MUX_PAD_EQOS_TD0_PE1, 0, P_PUSHPULL,
187 GPIO_PE2, MUX_PAD_EQOS_TD1_PE2, 0, P_PUSHPULL,
188 GPIO_PE3, MUX_PAD_EQOS_TD2_PE3, 0, P_PUSHPULL,
189 GPIO_PE4, MUX_PAD_EQOS_TD3_PE4, 0, P_PUSHPULL,
190 GPIO_PE5, MUX_PAD_EQOS_TX_CTL_PE5, 0, P_PUSHPULL),
193 GPIO_PF5, MUX_PAD_EQOS_MDC_PF5, 0, P_PUSHPULL),
249 /* Set output driver to pushpull if P_PUSHPULL. */
250 if (desc->flags & P_PUSHPULL) {
270 if (desc->flags & P_PUSHPULL) {
300 if (desc->flags & P_PUSHPULL) {