drivers/pinctrl/pinctrl-oxnas.c

61  * @groups: corresponding pin groups
113  * struct oxnas_pmx_pin - describes an pin mux
114  * @bank: the bank of the pin
115  * @pin: the pin number in the @bank
116  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
117  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
121 	uint32_t	pin;
127  * struct oxnas_pin_group - describes an pin group
128  * @name: the name of this specific pin group
129  * @pins_conf: the mux mode for each pin in this group. The size of this
132  *	from the driver-local pin enumeration space
300 static inline int pin_to_bank(unsigned pin)
302 	return pin / MAX_NB_GPIO_PER_BANK;
305 static unsigned pin_to_mask(unsigned int pin)
307 	return 1 << pin;
316 static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin)
318 	return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
319 		(readl_relaxed(pio + PULL_SENSE) & BIT(pin));
332 static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin)
334 	return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
335 			(!(readl_relaxed(pio + PULL_SENSE) & BIT(pin)));
349 static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
352 	return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin);
439 			  const struct oxnas_pmx_pin *pin)
441 	if (pin->mux) {
444 			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A',
445 			pin->conf);
448 			pin->bank + 'A', pin->pin, pin->conf);
453 			    int index, const struct oxnas_pmx_pin *pin)
458 	if (pin->bank >= info->nbanks) {
459 		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
460 			name, index, pin->bank, info->nbanks);
464 	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
465 		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
466 			name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
470 	if (!pin->mux)
473 	mux = pin->mux - 1;
476 		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
481 	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
482 		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
483 			name, index, mux, pin->bank + 'A', pin->pin);
512 	const struct oxnas_pmx_pin *pin;
525 		pin = &pins_conf[i];
526 		ret = pin_check_config(info, info->groups[group].name, i, pin);
532 		pin = &pins_conf[i];
533 		oxnas_pin_dbg(info->dev, pin);
535 		pio = pin_to_gpioctrl(info, pin->bank);
536 		cio = pin_to_muxctrl(info, pin->bank);
538 		mask = pin_to_mask(pin->pin);
541 		switch (pin->mux) {
561 		if (pin->mux)
615 	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
619 	dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n",
633 	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
634 	/* Set the pin to some default state, GPIO is usually default */
651 	unsigned pin;
657 	pin = pin_id % MAX_NB_GPIO_PER_BANK;
659 	if (oxnas_mux_get_pullup(pio, pin))
662 	if (oxnas_mux_get_pulldown(pio, pin))
665 	if (oxnas_mux_get_debounce(pio, pin, &div))
783 	struct oxnas_pmx_pin *pin;
794 	 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
807 	pin = grp->pins_conf = devm_kzalloc(info->dev,
816 		pin->bank = be32_to_cpu(*list++);
817 		pin->pin = be32_to_cpu(*list++);
818 		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
819 		pin->mux = be32_to_cpu(*list++);
820 		pin->conf = be32_to_cpu(*list++);
822 		oxnas_pin_dbg(info->dev, pin);
823 		pin++;
1109 		unsigned pin = chip->base + i;
1110 		unsigned mask = pin_to_mask(pin);
1140  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1265 	int pin = oxnas_gpio->chip.base + intspec[0];
1272 	ret = gpio_request(pin, ctrlr->full_name);
1276 	ret = gpio_direction_input(pin);