io/px/px_err.c

123 #define	JBC_BIT_DESC(bit, hdl, erpt) \
127 	PX_ERPT_SEND(erpt), \
132 	PX_ERPT_SEND(erpt), \
191 #define	UBC_BIT_DESC(bit, hdl, erpt) \
195 	PX_ERPT_SEND(erpt), \
200 	PX_ERPT_SEND(erpt), \
232 #define	IMU_BIT_DESC(bit, hdl, erpt) \
236 	PX_ERPT_SEND(erpt), \
241 	PX_ERPT_SEND(erpt), \
264 #define	MMU_BIT_DESC(bit, hdl, erpt) \
268 	PX_ERPT_SEND(erpt), \
273 	PX_ERPT_SEND(erpt), \
298 #define	ILU_BIT_DESC(bit, hdl, erpt) \
302 	PX_ERPT_SEND(erpt), \
307 	PX_ERPT_SEND(erpt), \
321 #define	TLU_UC_BIT_DESC(bit, hdl, erpt) \
325 	PX_ERPT_SEND(erpt), \
330 	PX_ERPT_SEND(erpt), \
332 #define	TLU_UC_OB_BIT_DESC(bit, hdl, erpt) \
336 	PX_ERPT_SEND(erpt), \
341 	PX_ERPT_SEND(erpt), \
374 #define	TLU_CE_BIT_DESC(bit, hdl, erpt) \
378 	PX_ERPT_SEND(erpt), \
383 	PX_ERPT_SEND(erpt), \
398 #define	TLU_OE_BIT_DESC(bit, hdl, erpt) \
402 	PX_ERPT_SEND(erpt), \
407 	PX_ERPT_SEND(erpt), \
409 #define	TLU_OE_OB_BIT_DESC(bit, hdl, erpt) \
413 	PX_ERPT_SEND(erpt), \
418 	PX_ERPT_SEND(erpt), \
474 #define	LPUL_BIT_DESC(bit, hdl, erpt) \
487 #define	LPUP_BIT_DESC(bit, hdl, erpt) \
500 #define	LPUR_BIT_DESC(bit, hdl, erpt) \
513 #define	LPUX_BIT_DESC(bit, hdl, erpt) \
526 #define	LPUS_BIT_DESC(bit, hdl, erpt) \
539 #define	LPUG_BIT_DESC(bit, hdl, erpt) \
951 		/* For each known bit in the register send erpt and handle */
1167 /* UBC FATAL - see io erpt doc, section 1.1 */
1945 /* PEC ILU none - see io erpt doc, section 3.1 */
2149 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */
2172 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */
2199 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */
2266 /* TLU Other Event - see io erpt doc, section 3.9 */