io/pci/pcisch.c

79 static void tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p,
1011 pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index)
1017 	uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no;
1040 	DEBUG3(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip,
1047 pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx)
1052 	uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no;
1054 	DEBUG1(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip,
1184 pci_iommu_setup(iommu_t *iommu_p)
1190 	pci_t *pci_p = iommu_p->iommu_pci_p;
1199 		iommu_p->iommu_mtlb_nreq = 0;
1200 		iommu_p->iommu_mtlb_npgs = 0;
1201 		iommu_p->iommu_mtlb_maxpgs = tm_mtlb_maxpgs;
1202 		iommu_p->iommu_mtlb_req_p = (dvma_unbind_req_t *)
1205 		mutex_init(&iommu_p->iommu_mtlb_lock, NULL, MUTEX_DRIVER, NULL);
1218 	iommu_p->iommu_dvma_end = dvma_prop->dvma_base +
1225 	iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size);
1226 	iommu_p->iommu_ctx_bitmap =
1228 	*iommu_p->iommu_ctx_bitmap = 1ull;	/* reserve context 0 */
1236 	iommu_p->iommu_flush_ctx_reg =
1239 		iommu_p->iommu_tfar_reg =
1245 pci_iommu_teardown(iommu_t *iommu_p)
1248 		iommu_ctx_free(iommu_p);
1249 	if (iommu_p->iommu_mtlb_req_p) {
1250 		kmem_free(iommu_p->iommu_mtlb_req_p,
1252 		mutex_destroy(&iommu_p->iommu_mtlb_lock);
1253 		iommu_p->iommu_mtlb_req_p = NULL;
1254 		iommu_p->iommu_mtlb_nreq = 0;
1255 		iommu_p->iommu_mtlb_npgs = iommu_p->iommu_mtlb_maxpgs = 0;
2143 	iommu_t *iommu_p = pci_p->pci_iommu_p;
2153 	if (!((stat = *iommu_p->iommu_ctrl_reg) & TOMATILLO_IOMMU_ERR)) {
2578 	iommu_t *iommu_p = pci_p->pci_iommu_p;
2595 	pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg;
2641 		pbm_err_p->pbm_iommu.iommu_tfar = *iommu_p->iommu_tfar_reg;
2668 	iommu_t *iommu_p = pci_p->pci_iommu_p;
2679 	*iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat;
2925 iommu_ctx_free(iommu_t *iommu_p)
2927 	kmem_free(iommu_p->iommu_ctx_bitmap, IOMMU_CTX_BITMAP_SIZE);
2938 iommu_tlb_scrub(iommu_t *iommu_p, int scrub)
2941 	dev_info_t *dip = iommu_p->iommu_pci_p->pci_dip;
2944 	uint64_t base = (uint64_t)iommu_p->iommu_ctrl_reg -
2999 pci_iommu_disp(iommu_t *iommu_p, uint64_t *ctl_p)
3002 	if (CHIP_TYPE(iommu_p->iommu_pci_p) != PCI_CHIP_TOMATILLO)
3005 	ctl_old = *iommu_p->iommu_ctrl_reg;
3013 	if (iommu_p->iommu_tsb_size != TOMATILLO_IOMMU_TSB_MAX)
3018 	return (3 << (iommu_p->iommu_dvma_base >> (32 - 3)));
3022 pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa)
3024 	uintptr_t pbm_regbase = get_pbm_reg_base(iommu_p->iommu_pci_p);
3030 	volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg;
3031 	volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr;
3032 	volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg;
3033 	uint64_t mask = pci_iommu_disp(iommu_p, &iommu_ctl);
3035 	DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip,
3038 	DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip,
3041 	DEBUG4(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip,
3056 	if (!(CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_XMITS))
3579 tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, dvma_addr_t dvma_pg,
3584 	dvma_unbind_req_t *req_base_p = iommu_p->iommu_mtlb_req_p;
3590 	mutex_enter(&iommu_p->iommu_mtlb_lock);
3592 	iommu_p->iommu_mtlb_npgs += npages;
3593 	req_max_p = req_base_p + iommu_p->iommu_mtlb_nreq++;
3599 	if (iommu_p->iommu_mtlb_npgs <= iommu_p->iommu_mtlb_maxpgs)
3603 	reg_base = iommu_p->iommu_pci_p->pci_address[0];
3621 			pci_vmem_do_free(iommu_p,
3624 			iommu_p->iommu_mtlb_npgs -= req_p->dur_npg;
3633 	iommu_p->iommu_mtlb_nreq = preserv_count;
3635 	mutex_exit(&iommu_p->iommu_mtlb_lock);
3639 pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr,
3643 		tm_vmem_free(mp, iommu_p,
3646 		pci_vmem_do_free(iommu_p, dvma_addr, npages,