Lines Matching refs:DEF_INVALID_REG_VAL
81 #define DEF_INVALID_REG_VAL -1
164 static int8_t p_latency_timer = DEF_INVALID_REG_VAL;
175 static int8_t p_cache_line_size = DEF_INVALID_REG_VAL;
190 static int8_t p_pwrite_threshold = DEF_INVALID_REG_VAL;
197 static int8_t s_pwrite_threshold = DEF_INVALID_REG_VAL;
209 static int8_t p_dread_threshold = DEF_INVALID_REG_VAL;
221 static int8_t s_dread_threshold = DEF_INVALID_REG_VAL;
230 static int8_t delayed_trans_order = DEF_INVALID_REG_VAL;
794 if ((dbp->p_latency_timer != (int8_t)DEF_INVALID_REG_VAL) &&
799 if ((dbp->s_latency_timer != (int8_t)DEF_INVALID_REG_VAL) &&
804 if ((dbp->p_cache_line_size != (int8_t)DEF_INVALID_REG_VAL) &&
809 if ((dbp->s_cache_line_size != (int8_t)DEF_INVALID_REG_VAL) &&
814 if ((dbp->p_pwrite_threshold != (int8_t)DEF_INVALID_REG_VAL) &&
822 if ((dbp->s_pwrite_threshold != (int8_t)DEF_INVALID_REG_VAL) &&
831 if ((dbp->p_dread_threshold != (int8_t)DEF_INVALID_REG_VAL) &&
841 if ((dbp->s_dread_threshold != (int8_t)DEF_INVALID_REG_VAL) &&
850 if ((dbp->delayed_trans_order != (int8_t)DEF_INVALID_REG_VAL) &&