sun4u/cpu/us3_common_asm.s

192 	 * %o1 = sfmmup
211         cmp     %o3, %o1
227 	 * %o1 = sfmmup
230 	SFMMU_CPU_CNUM(%o1, %g1, %g2)		! %g1 = sfmmu cnum on this CPU
232 	ldub	[%o1 + SFMMU_CEXT], %o4		! %o4 = sfmmup->sfmmu_cext
240 	srlx	%o2, CTXREG_NEXT_SHIFT, %o1	! need to preserve nucleus pgsz
241 	sllx	%o1, CTXREG_NEXT_SHIFT, %o1	! %o1 = nucleus pgsz
242 	or	%g1, %o1, %g1			! %g1 = nucleus pgsz | primary pgsz | cnum
475 	 * %o0 = pfnum, %o1 = color
477 	DCACHE_FLUSHPAGE(%o0, %o1, %o2, %o3, %o4)
520 	DCACHE_FLUSHCOLOR(%o0, 0, %o1, %o2, %o3)
521 	DCACHE_FLUSHCOLOR(%o0, 1, %o1, %o2, %o3)
522 	DCACHE_FLUSHCOLOR(%o0, 2, %o1, %o2, %o3)
523 	DCACHE_FLUSHCOLOR(%o0, 3, %o1, %o2, %o3)
604  *	%o1, %o2 - arguments (2 uint64_t's)
635 	stxa	%o1, [%g2]ASI_INTR_DISPATCH
667 	sll	%o1, IDCR_BN_SHIFT, %g2		! IDCR<28:24> = b/n pair
694  *	%o1 bytes to be flushed
751  *	%o1 - ecache size
774 	ECACHE_FLUSHALL(%o1, %o2, %o0, %o4)
795 	ASM_LD(%o1, dcache_linesize)
796 	CH_DCACHE_FLUSHALL(%o0, %o1, %o2)
814 	ld	[%o0 + CHPR_ICACHE_LINESIZE], %o1
819 	ASM_LD(%o1, icache_linesize)
821 	CH_ICACHE_FLUSHALL(%o0, %o1, %o2, %o4)
840 	CH_DCACHE_FLUSHALL(%o0, %o1, %g1)
858 	PCACHE_FLUSHALL(%o0, %o1, %o2)
888 	  stx	%o0, [%o1 + CH_DC_IDX]
893 	stx	%o2, [%o1 + CH_DC_TAG]
897 	stx	%o2, [%o1 + CH_DC_UTAG]
899 	stx	%o2, [%o1 + CH_DC_SNTAG]
900 	add	%o1, CH_DC_DATA, %o1
906 	stx	%o2, [%o1 + %o3]
934 	add	%o1, CH_DC_PN_DATA_PARITY - CH_DC_DATA + 7, %o1
944 	stb	%o2, [%o1]
945 	dec	%o1
979 	stx	%o0, [%o1 + CH_IC_IDX]
981 	stx	%o2, [%o1 + CH_IC_PATAG]
985 	stx	%o2, [%o1 + CH_IC_UTAG]
988 	stx	%o2, [%o1 + CH_IC_UPPER]
991 	stx	%o2, [%o1 + CH_IC_LOWER]
993 	stx	%o2, [%o1 + CH_IC_SNTAG]
994 	add	%o1, CH_IC_DATA, %o1
998 	stx	%o2, [%o1 + %o3]
1033 	stx	%o0, [%o1 + CH_PC_IDX]
1035 	stx	%o2, [%o1 + CH_PC_STATUS]
1037 	stx	%o2, [%o1 + CH_PC_TAG]
1039 	stx	%o2, [%o1 + CH_PC_SNTAG]
1040 	add	%o1, CH_PC_DATA, %o1
1044 	stx	%o2, [%o1 + %o3]
2347 	stx	%g1, [%o1]
2370 	stx	%g1, [%o1]
2491 	 * %o1 = input D$ line size
2497 	sub	%o0, %o1, %o0			! init cache line address
2522 	sub	%o1, 8, %o2
2539 	subcc	%o0, %o1, %o0
2598 	add	%g4, %o0, %o1		! adjust stick with skew
2599 	wr	%o1, %g0, STICK		! write stick reg
2683  *	%o1 - scratch
2737 	ld	[%o0 + CHPR_ICACHE_LINESIZE], %o1
2742 	ASM_LD(%o1, icache_linesize)
2744 	CH_ICACHE_FLUSHALL(%o0, %o1, %o2, %o4)
2816 	ldxa	[%o2]ASI_AFSR, %o1		! shadow afsr reg
2817 	stx	%o1, [%o0 + CH_CPU_ERRORS_SHADOW_AFSR]
2818 	ldxa	[%o2]ASI_AFAR, %o1		! shadow afar reg
2819 	stx	%o1, [%o0 + CH_CPU_ERRORS_SHADOW_AFAR]
2825 	ldxa	[%o2]ASI_AFSR, %o1		! afsr_ext reg
2826 	stx	%o1, [%o0 + CH_CPU_ERRORS_AFSR_EXT]
2828 	ldxa	[%o2]ASI_AFSR, %o1		! shadow afsr_ext reg
2829 	stx	%o1, [%o0 + CH_CPU_ERRORS_SHADOW_AFSR_EXT]
2847 	ldxa	[%o2]ASI_MCU_CTRL, %o1
2848 	stx	%o1, [%o0 + CH_CPU_ERRORS_AFAR2]
2850 	ldxa	[%g0]ASI_AFSR, %o1		! primary afsr reg
2851 	stx	%o1, [%o0 + CH_CPU_ERRORS_AFSR]
2852 	ldxa	[%g0]ASI_AFAR, %o1		! primary afar reg
2854 	stx	%o1, [%o0 + CH_CPU_ERRORS_AFAR]
2903 	mov	CE_CEEN_TIMEOUT, %o1
2936 	add	%o1, CH_CLO_DATA + CH_CHD_EC_DATA, %o1
2939 	GET_ECACHE_DTAGS(%o0, %o1, %o3, %o4, %o5)
3039 	subcc	%o1, %o2, %o1
3040 	add	%o0, %o1, %o3
3075 	CPU_INDEX(%o0, %o1)
3077 	set  cpunodes + DEVICE_ID, %o1
3079 	stx  %o2, [%o0 + %o1]
3106 	stx	%o2, [%o1]
3107 	stx	%o3, [%o1 + 8 ]
3140 	ldxa	[%g0]ASI_ITLB_ACCESS, %o1	! %o1 = entry 0 data
3143 	cmp	%o1, %g0			! Is this entry valid?
3145 	  andcc	%o1, TTE_LCK_INT, %g0		! Is this entry locked?
3184 	stxa	%o1, [%g3]ASI_ITLB_ACCESS
3213 	ldxa	[%g0]ASI_DTLB_ACCESS, %o1	! %o1 = entry 0 data
3216 	cmp	%o1, %g0			! Is this entry valid?
3218 	  andcc	%o1, TTE_LCK_INT, %g0		! Is this entry locked?
3253 	stxa	%o1, [%g3]ASI_DTLB_ACCESS