5  * Common Development and Distribution License (the "License").
11  * and limitations under the License.
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
175  * Cheetah MMU and Cache operations.
293 	 * x-trap to flush page from tlb and tsb
357 	 *	that interrupts are disabled and this code is
363 	and	%g4, %g2, %g3			/* g3 = pgcnt - 1 */
878  * Get dcache data and tag.  The Dcache data is a pointer to a ch_dc_data_t
925 	 * and add the offset of the last parity byte since we will be
967  * Get icache data and tag.  The data argument is a pointer to a ch_ic_data_t
1019  * Get pcache data and tags.
1022  *		  registers. Contains PC_way and PC_addr shifted into
1067  * re-enable the i$, d$, w$, and p$ according to bootup cache state.
1068  * Turn on WE, HPE, SPE, PE, IC, and DC bits defined as DCU_CACHE.
1107  * Fast ECC at TL>0 error trap handler and, on Cheetah+, by both the Fast
1108  * ECC at TL>0 error and the I$/D$ parity error at TL>0 trap handlers.
1109  * NB: Must be 8 instructions or less to fit in trap table and code must
1142 	 * non-zero, then an error has occurred and it is handled.
1144 	 * an error is detected pil_interrupt will not be called and
1195  * the CPU, External Cache, Cheetah Data Switch and system bus. Error
1196  * information is logged in the AFSR, (also AFSR_EXT for Panther) and
1197  * AFAR and one of the following traps is generated (provided that it
1202  * 2. trap 0x0A and 0x32: Deferred trap
1215  * Software must handle single and multi bit errors which occur due to data
1221  * 1) Record the state and then turn off the Dcache and Icache.  The Dcache
1229  * 4) Read the AFAR and AFSR.
1232  *    7) Capture Ecache, Dcache and Icache lines in "CPU log out" structure.
1233  *    8) Flush Ecache then Flush Dcache and Icache and restore to previous
1240  *    8) Flush Ecache then Flush Dcache and Icache and restore to previous
1244  *       finding this error bit and logging information about it later.
1245  * 7) Alternatively (to 5 and 6 above), if the cpu_private struct is not
1247  *    we place the clo_flags data into %g2 (sys_trap->have_win arg #1) and
1249  *    to determine information such as TL, TT, CEEN and NCEEN settings, etc
1254  * We flush the E$ and D$ here on TL=1 code to prevent getting nested
1262  * the Fast ECC at TL>0 handler and eventually Red Mode.
1264  * Note that for Cheetah (and only Cheetah), we use alias addresses for
1268  * it's the largest piece of memory we touch in the handler and it is
1277  * NB: Must be 8 instructions or less to fit in trap table and code must
1293 	 * Save current DCU state.  Turn off the Dcache and Icache.
1321 	 * Turn off CEEN and NCEEN.
1333 	 * we had to park the core (%g1 holds our DCUCR value and
1336 	 * or not to unpark later. %g5 and %g4 are scratch registers.
1353 	 /* store the CEEN and NCEEN values, TL=0 */
1354 	and	%g3, EN_REG_CEEN + EN_REG_NCEEN, %g4
1359 	 * Flush the Ecache (and L2 cache for Panther) to get the error out
1385 	 * Icache line it is now stale or corrupted and we must flush it
1402 	 * whether or not we need to unpark. %g5 and %g4 are scratch registers.
1407 	 * Restore the Dcache and Icache to the previous state.
1421 	 * we tried to use it and failed (nesting count)? If we have
1423 	 * assume things are not going to get better by themselves and
1437 	 * issue a retry. Our TL=0 trap handler code will check and
1439 	 * in the logout struct and handle this event at that time.
1467  *    will use to save %g1 and %g2.
1469  *    we save %g1+%g2 using %tpc, %tnpc + %tstate and jump to the fast ecc
1471  * 3) Turn off the Dcache if it was on and save the state of the Dcache
1479  * 7) Save the appropriate flags and TPC in the ch_err_tl1_data structure.
1481  * 9) For Cheetah and Jalapeno, read the AFAR and AFSR and clear.  For
1482  *    Cheetah+ (and later), read the shadow AFAR and AFSR but don't clear.
1484  *    AFSR_EXT and save the value in ch_err_tl1_data.
1492  * 13) For Cheetah and Jalapeno, read the AFAR and AFSR and clear again.
1493  *    For Cheetah+ (and later), read the primary AFAR and AFSR and now clear.
1495  *    read and clear the primary AFSR_EXT and save it in ch_err_tl1_data.
1496  * 14) Flush and re-enable the Dcache if it was on at step 3.
1501  *    event pending flag and call cpu_tl1_error via systrap if set.
1502  * 19) Restore the registers from step 5 and issue retry.
1509  * which goes to fecc_err_tl1_cont_instr, and we continue the handling there.
1510  * NB: Must be 8 instructions or less to fit in trap table and code must
1534  * and %g2.  Note that %tstate has bits 0-2 and then bits 8-19 as r/w,
1535  * there's a reserved hole from 3-7.  We only use bits 0-1 and 8-9 (the low
1536  * order two bits from %g1 and %g2 respectively).
1537  * NB: Must be 8 instructions or less to fit in trap table and code must
1577  *    THCE		(CEEN and ET_ECC_en controlled)
1583  *    TUE_SH, TUE		(NCEEN and L2_tag_ECC_en controlled)
1584  *    L3_TUE, L3_TUE_SH		(NCEEN and ET_ECC_en controlled)
1585  *    THCE			(CEEN and L2_tag_ECC_en controlled)
1586  *    L3_THCE			(CEEN and ET_ECC_en controlled)
1595  *		5. Capture Ecache, Dcache and Icache lines associated
1601  *		5. Incriment "logout busy count" and place into %g3
1604  *		   code will end up finding this error bit and logging
1606  *	5. Alternatively (to 3 and 4 above), if the cpu_private struct is
1609  *         (sys_trap->have_win arg #1) and call cpu_disrupting_error via
1646 	 * we had to park the core (%g1 holds our DCUCR value and
1649 	 * or not to unpark later. %g5 and %g4 are scratch registers.
1672 	 * Icache line it is now stale or corrupted and we must flush it
1689 	 * whether or not we need to unpark. %g5 and %g4 are scratch registers.
1708 	 * we tried to use it and failed (nesting count)? If we have
1710 	 * assume things are not going to get better by themselves and
1724 	 * issue a retry. Our TL=0 trap handler code will check and
1726 	 * in the logout struct and handle this event at that time.
1748  * actually be called and so we treat this like a BAD TRAP panic.
1777  * (instruction_access_error) and 0x32 (data_access_error) at TL>=0.
1788  *	1. Disable CEEN and NCEEN errors to prevent recursive errors.
1796  *		6. Capture Ecache, Dcache and Icache lines associated
1804  *		   code will end up finding this error bit and logging
1806  *      6. Alternatively (to 4 and 5 above), if the cpu_private struct is
1809  *         (sys_trap->have_win arg #1) and call cpu_deferred_error via
1823 	 * Disable CEEN and NCEEN.
1835 	 * Disable Dcache for both Data Access Error and Instruction Access
1848 	 * we had to park the core (%g1 holds our DCUCR value and
1851 	 * or not to unpark later. %g6 and %g4 are scratch registers.
1875 	and	%g4, %g2, %g4			! ttype
1876 	or	%g6, %g4, %g4			! TT and TL
1877 	and	%g3, EN_REG_CEEN, %g3		! CEEN value
1878 	or	%g3, %g4, %g4			! TT and TL and CEEN
1884 	 * TT, TL, and CEEN information to the TL=0 handler via 
1895 	 * Icache line it is now stale or corrupted and we must flush it
1924 	 * whether or not we need to unpark. %g5 and %g7 are scratch registers.
1929 	 * Restore Icache and Dcache to previous state.
1943 	 * we tried to use it and failed (nesting count)? If we have
1945 	 * assume things are not going to get better by themselves and
1959 	 * issue a retry. Our TL=0 trap handler code will check and
1961 	 * in the logout struct and handle this event at that time.
1980  * arguments for cpu_parity_error and calls it via sys_trap.
1981  * NB: Must be 8 instructions or less to fit in trap table and code must
2008  * Trap 1" at TL>0, which goes to dcache_parity_tl1_cont_instr, and we
2010  * NB: Must be 8 instructions or less to fit in trap table and code must
2033  * and %g2.  Note that %tstate has bits 0-2 and then bits 8-19 as r/w,
2034  * there's a reserved hole from 3-7.  We only use bits 0-1 and 8-9 (the low
2035  * order two bits from %g1 and %g2 respectively).
2036  * NB: Must be 8 instructions or less to fit in trap table and code must
2055  * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
2069 	 * structure, updates the ch_err_tl1_flags and saves the %tpc in
2071 	 * the ch_err_tl1_data structure and %g2 will have the original
2073 	 * except for %g1 and %g2 will be available.
2131 	 * I$ and D$ are automatically turned off by HW when the CPU hits
2135 	 * and HW does not automatically disable P$, we need to disable it
2148 	 * the ch_err_tl1_data structure and want the PIL15 softint to pick
2149 	 * it up and log it.  %g1 must point to the ch_err_tl1_data structure.
2150 	 * Restores the %g registers and issues retry.
2161  * arguments for cpu_parity_error and calls it via sys_trap.
2162  * NB: Must be 8 instructions or less to fit in trap table and code must
2189  * Trap 2" at TL>0, which goes to icache_parity_tl1_cont_instr, and we
2191  * NB: Must be 8 instructions or less to fit in trap table and code must
2213  * and %g2.  Note that %tstate has bits 0-2 and then bits 8-19 as r/w,
2214  * there's a reserved hole from 3-7.  We only use bits 0-1 and 8-9 (the low
2215  * order two bits from %g1 and %g2 respectively).
2216  * NB: Must be 8 instructions or less to fit in trap table and code must
2236  * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
2250 	 * structure, updates the ch_err_tl1_flags and saves the %tpc in
2252 	 * the ch_err_tl1_data structure and %g2 will have the original
2254 	 * except for %g1 and %g2 will be available.
2313 	 * the ch_err_tl1_data structure and want the PIL15 softint to pick
2314 	 * it up and log it.  %g1 must point to the ch_err_tl1_data structure.
2315 	 * Restores the %g registers and issues retry.
2327  * The itlb_rd_entry and dtlb_rd_entry functions return the tag portion of the
2328  * tte, the virtual address, and the ctxnum of the specified tlb entry.  They
2432 	 * ensure that the read and write instructions are in the same
2475  * Correct D$ data parity by zeroing the data and initializing microtag
2476  * for all indexes and all ways of the D$.
2520 	 * Zero line of D$ data (and data parity bits for Panther)
2634  *	%o0 - index for the invalidation, specifies DC_way and DC_addr
2637  * stored to a particular DC_way and DC_addr in ASI_DC_TAG.
2647  * DC_valid is the 1-bit valid field for both the physical and snoop tags.
2649  * The format of the 64-bit DC_way and DC_addr into ASI_DC_TAG is:
2659  * Setting the DC_valid bit to zero for the specified DC_way and
2669 	sll	%o0, 5, %o0		! shift index into DC_way and DC_addr
2670 	stxa	%g0, [%o0]ASI_DC_TAG	! zero the DC_valid and DC_tag bits
2684  *	%o2 - used to save and restore DCU value
2686  *	%o5 - used to save and restore PSTATE
2689  * the I$ should be turned off. Accesses to ASI_IC_TAG may collide and
2690  * block out snoops and invalidates to the I$, causing I$ consistency
2705  * Valid is the 1-bit valid field for both the physical and snoop tags.
2720  *	as containing Valid and IC_vpred as described above.
2722  * Setting the Valid bit to zero for the specified IC_way and
2762  * crosstrap.  It atomically increments the outstanding request counter and,
2883 					! and divide by 64
2894 	! if error, read the error regs and log it
2922  * sure cpu private area exists and that the indicated logout area is free
2923  * for use, and that we are unable to migrate cpus.
3071 	! get the device_id and store the device_id
3157 	! loads its text page at index 15 in sfmmu_kernel_remap() and we

Indexes created Tue Aug 27 01:24:33 MDT 2024