sun4u/cpu/opl_olympus_asm.s

5  * Common Development and Distribution License (the "License").
11  * and limitations under the License.
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
67  * SPARC64-VI MMU and Cache operations.
186 	 * x-trap to flush page from tlb and tsb
250 	 *	that interrupts are disabled and this code is
256 	and	%g4, %g2, %g3			/* g3 = pgcnt - 1 */
744 	and	logpa, bufmask, logpa				;\
830 	and	tmp1, tmp2, tmp1				;\
985  * and we reset these regiseter here.
1057  * 0 in the IV field disabling the shared context support, and
1089  * sys_trap() and user_trap() to work consistently. So we have to force
1095  * an inconsistent state, we need to do a stack reset and switch to
1097  * We also reset the window registers and MMU registers just to
1100  * To set regular %g7, we need to clear PSTATE_AG bit and need to
1101  * use one local register. Note that we are panicking and will never
1233  * All TL=0 and TL>0 0xA and 0x32 traps vector to this handler.
1237  * 2. The SFSR register is read and verified as valid by checking
1239  *    error cases cannot be decoded/determined and the SFPAR
1253  *	restore globals and retry (no ereport is generated).
1257  *	Flush all tlbs and generate ereport.
1258  * 3. TL=0 and TL>0 considerations
1262  *	in the handler and the system is assumed to eventually
1271  *        when a UE was originally detected in user stack and
1274  *        condition (TL>1 and UE error), paranoid code is added
1295 	bz,a,pn %xcc, 2f		! Branch if SFSR is invalid and
1300 	bz,a,pt %xcc, 1f		! Branch if not UE/BERR/TO and
1323 	 * This is the TLB parity error case and it is the
1325 	 * Only %g1, %g2 and %g3 are allowed
1330 	and	%g3, ERRLOG_REG_NUMERR_MASK, %g3! Extract the error count
1363 	 * - SFSR_FV is valid and SFSR_UE is set
1413  * All TL=0 and TL>0 0x40 traps vector to this handler.
1416  *    Faultaddress is N/A here and it is not collected.
1419  *    to prevent any potential error storms and branch directly
1441  * 4. The rest of the error cases are unrecoverable and will
1477 	 * 1. Error trap came from TL=0 and
1488 	and	%g2, 3, %g2		! extract the shifted [1:0] bits
1494 	and	%g2, ERRLOG_REG_NUMERR_MASK, %g3! Extract error count and
1499 	set	OPL_SCRATCHPAD_ERRLOG, %g3	! and write back the updated
1692  * stack can get unmapped between the flushw and restore instructions
1740  * The actual trap handler for tt=0x0a, and tt=0x32
1995 	and	%o2, %o1, %o3
2022 	 * sITLB and sDTLB.
2052 	! get the device_id and store the device_id
2081 	 * ensure that the read and write instructions are in the same