Lines Matching refs:o2

217 	mov	ls2, %o2;						\
350 * %o2 = pil
363 * %o2 = cpu
370 mov %o2, %l1
377 ldn [THREAD_REG + T_CPU], %o2 ! delay - load CPU pointer
415 lduh [%o2 + CPU_DIVISOR], %l2 ! delay -- %l2 = clock divisor
426 ldx [%o2 + %l3], %o5 ! old counter in o5
428 stx %o5, [%o2 + %l3] ! store new counter
431 lduh [%o2 + CPU_MSTATE], %l3
434 add %l3, %o2, %l3
453 ldn [%o2 + CPU_INTR_THREAD], %o3 ! interrupt thread pool
455 stn %o4, [%o2 + CPU_INTR_THREAD]
459 ld [%o2 + CPU_INTR_ACTV], %o5
480 st %o5, [%o2 + CPU_INTR_ACTV]
503 stn %o3, [%o2 + CPU_THREAD] ! set new thread
532 ld [%o2 + CPU_FTRACE_STATE], %o4 ! %o2 = curthread->t_cpu
542 mov %i1, %o2
551 SERVE_INTR_PRE(%o1, %o2, %l1, %l3, %o4, %o5, %o3, %o0)
556 SERVE_INTR(%o1, %o2, %l1, %l3, %o4, %o5, %o3, %o0)
607 lduh [%o2 + CPU_DIVISOR], %o0 ! delay -- %o0 = clock divisor
621 add %o1, %o2, %o1
632 lduh [%o2 + CPU_MSTATE], %o1
635 add %o1, %o2, %o1
662 lduh [%o2 + CPU_FLAGS], %o5 ! don't preempt if quiesced
669 ldub [%o2 + CPU_INTRCNT], %o5 ! delay - %o5 = cpu_intrcnt
673 stub %o5, [%o2 + CPU_INTRCNT] ! delay annul - inc CPU_INTRCNT
680 stub %o4, [%o2 + CPU_KPRUNRUN]
681 ldx [%o2 + CPU_STATS_SYS_INTRUNPIN], %o4
683 stx %o4, [%o2 + CPU_STATS_SYS_INTRUNPIN]
685 stub %o5, [%o2 + CPU_INTRCNT] ! delay
688 ldub [%o2 + CPU_KPRUNRUN], %o5
692 mov %o2, %l3 ! delay - save %o2
695 mov %l3, %o2 ! restore %o2
703 ld [%o2 + CPU_INTR_ACTV], %o5 ! delay annulled
708 ld [%o2 + CPU_BASE_SPL], %o4
712 SERVE_INTR_NEXT(%o1, %o2, %l1, %l3, %o4, %o5, %o3, %o0)
739 st %o5, [%o2 + CPU_INTR_ACTV]
751 ldn [%o2 + CPU_INTR_THREAD], %o3
753 stn THREAD_REG, [%o2 + CPU_INTR_THREAD]
762 stn %o4, [%o2 + CPU_THREAD]
791 stub %g0, [%o2 + CPU_INTRCNT] ! delay annul
825 ld [%o2 + CPU_BASE_SPL], %o5
834 ldx [%o2 + CPU_STATS_SYS_INTRBLK], %o4
836 stx %o4, [%o2 + CPU_STATS_SYS_INTRBLK]
848 ld [%o2 + CPU_INTR_ACTV], %o5
865 ld [%o2 + CPU_INTR_ACTV], %o5 ! delay - load active mask
875 ldn [%o2 + CPU_INTR_THREAD], %o5 ! get list pointer
878 stn THREAD_REG, [%o2 + CPU_INTR_THREAD] ! delay - put thread on list
904 * %o2 = pil
940 sub %o2, LOCK_LEVEL + 1, %o5
943 stn %l2, [%o3 + %o4] ! save onfault label for pil %o2
945 stn %l3, [%o3 + %o4] ! save lofault data for pil %o2
952 sub %o2, LOCK_LEVEL + 1, %o5
955 stn %l2, [%o3 + %o4] ! save on_trap label for pil %o2
962 sll %o4, %o2, %o4 ! construct mask for level
993 ! o2 = PIL of this interrupt
1003 sub %o2, LOCK_LEVEL + 2, %o4
1139 ! ASSERT(%o2 > LOCK_LEVEL)
1141 cmp %o2, LOCK_LEVEL
1146 call cmn_err ! %o2 has the %pil already
1152 sub %o2, LOCK_LEVEL + 1, %o4 ! convert PIL to array index
1159 wrpr %g0, %o2, %pil ! enable interrupts
1164 SERVE_INTR_PRE(%o1, %o3, %l2, %l3, %o4, %o5, %o2, %o0)
1166 SERVE_INTR(%o1, %o3, %l2, %l3, %o4, %o5, %o2, %o0)
1168 brz,a,pt %o2, 0f ! if %o2, more intrs await
1169 rdpr %pil, %o2 ! delay annulled
1170 SERVE_INTR_NEXT(%o1, %o3, %l2, %l3, %o4, %o5, %o2, %o0)
1176 cmp %o2, PIL_15
1200 cmp %o2, PIL_14
1210 ! %o2 = PIL
1220 sll %o5, %o2, %o5
1242 sub %o2, LOCK_LEVEL + 1, %o4 ! PIL to array index
1271 sllx %o2, 4, %o4 ! PIL index to byte offset
1294 ! o2 = PIL
1314 sub %o2, LOCK_LEVEL + 2, %o5
1355 sub %o2, LOCK_LEVEL + 1, %o4
1383 wrpr %g0, %o2, %pil ! enable interrupts
1512 set (TICK_INT_MASK | STICK_INT_MASK), %o2
1513 andcc %l1, %o2, %g0
1517 CPU_ADDR(%o1, %o2)
1940 ldn [THREAD_REG + T_CPU], %o2 ! load CPU pointer
1941 ld [%o2 + CPU_INTR_ACTV], %o5 ! load active interrupts mask
1945 * %o2 = pointer to CPU
1976 st %o3, [%o2 + CPU_BASE_SPL] ! delay - store base priority
2025 ldn [%i2 + (10*GREGSIZE)], %o2
2047 stn %o2, [%i3 + STACK_BIAS + (10*GREGSIZE)]
2157 lduh [THREAD_REG + T_FLAGS], %o2
2158 andcc %o2, T_INTR_THREAD, %g0
2180 ! %o2 = scratch
2193 RD_CLOCK_TICK_NO_SUSPEND_CHECK(%o2, %o0)
2194 stx %o2, [THREAD_REG + T_INTR_START]
2195 sub %o2, %o3, %o0
2206 ldx [%o5 + %o4], %o2
2207 add %o2, %o0, %o2
2208 stx %o2, [%o5 + %o4]
2220 ldx [%o3], %o2
2221 add %o2, %o0, %o2 ! %o2 = new value for intrstat
2222 stx %o2, [%o3]
2224 sub %o2, %o4, %o0 ! %o0 is elapsed time since %o4
2225 stx %o2, [%o3 + 8] ! make [1] match [0], resetting time
2227 ld [%o5 + CPU_BASE_SPL], %o2 ! restore %pil to the greater
2228 cmp %o2, %o1 ! of either our pil %o1 or
2229 movl %xcc, %o1, %o2 ! cpu_base_spl.
2231 wrpr %g0, %o2, %pil